Three-dimensional memory device and method for manufacturing three-dimensional memory device
A three-dimensional memory device and a method for manufacturing the same are provided. The method includes steps as follows. A semiconductor structure including a substrate and a stacked structure on the substrate is provided. The stacked structure includes alternately stacked gate layers and dielectric layers, or alternately stacked dummy gate layers and dielectric layers. The dummy gate layers are replaceable by the gate layers. A groove is formed in a gate line slit region of the stacked structure. The groove penetrates through the gate layers and multiple layers of the dielectric layers, or through the dummy gate layers and multiple layers of the dielectric layers. An insulating layer is formed on a surface of the stacked structure and in the groove. A depression is formed on a surface of the insulating layer above the groove away from the substrate. The insulating layer is polished to flatten the depression.
1 . A three-dimensional memory device, comprising:
a substrate;
a stacked structure arranged on the substrate and comprising gate layers and dielectric layers, wherein the gate layers and the dielectric layers are alternately stacked;
gate line slits penetrating through the stacked structure to the substrate, wherein the gate line slits are separated by a separating structure;
an insulating layer disposed on the separating structure and extending outward from the separating structure to cover the stacked structure, wherein a surface of the insulating layer on the separating structure and a surface of the insulating layer on the stacked structure, deviating away from the substrate, are flat; and
a top selective gate cut extending in a first lateral direction and arranged over and aligned with a row of channel holes filled with a sacrificial layer.
2 . The three-dimensional memory device of claim 1 , wherein the insulating layer comprises a first insulating layer on the separating structure and a second insulating layer on the first insulating layer, wherein a surface of the second insulating layer deviating away from the first insulating layer is flat.
3 . The three-dimensional memory device of claim 1 , further comprising an array common source disposed in the gate line slits.
4 . The three-dimensional memory device of claim 3 , further comprising a connection bridge across the insulating layer, wherein the connection bridge connects the array common source spaced by the insulating layer.
5 . The three-dimensional memory device of claim 1 , wherein the insulating layer is disposed in a core region of the stacked structure.
6 . The three-dimensional memory device of claim 1 , wherein
the top selective gate cut extends through the gate layers and multiple layers of the dielectric layers in the stacked structure; and
the top selective gate cut comprises another insulating layer, wherein the other insulating layer in the top selective gate cut and the insulating layer on the separating structure are formed according to a same filling process.
7 . The three-dimensional memory device of claim 6 , wherein a material of the other insulating layer in the top selective gate cut and a material of the insulating layer in the separating structure are identical.
8 . The three-dimensional memory device of claim 7 , wherein the identical material is silicon oxide.
9 . The three-dimensional memory device of claim 6 , wherein in a second lateral direction perpendicular to the first lateral direction, a width of the separating structure is greater than a width of the top selective gate cut.
10 . The three-dimensional memory device of claim 1 , wherein in a vertical direction where the gate layers and the dielectric layers are alternately stacked, a thickness of the insulating layer on the separating structure is approximately between 150 nm and 250 nm.
11 . The three-dimensional memory device of claim 1 , further comprising:
channel structures in a core region of the stacked structure,
wherein the separating structure is disposed between the channel structures in a second lateral direction perpendicular to the first lateral direction, and one of the gate line slits is configured to extend, in the first lateral direction and a vertical direction that is perpendicular to the first and second lateral directions, between the channel structures.
12 . The three-dimensional memory device of claim 11 , wherein a conductive plug is arranged on top of each channel structure of the channel structures.
13 . The three-dimensional memory device of claim 12 , wherein a top surface of the conductive plug is flush with the surface of the insulating layer on the stacked structure.
14 . The three-dimensional memory device of claim 12 , wherein:
the insulating layer comprises a first insulating layer in the separating structure and a second insulating layer on the first insulating layer; and
a top surface of the conductive plug is higher than a top surface of the first insulating layer.
15 . The three-dimensional memory device of claim 11 , wherein the insulating layer is arranged between adjacent ones of the channel structures.
16 . The three-dimensional memory device of claim 1 , wherein:
the insulating layer of the separating structure comprises a first insulating layer and a second insulating layer; and
the three-dimensional memory device further comprises the top selective gate cut filled with the first insulating layer, the second insulating layer being disposed on the first insulating layer of the top selective gate cut.
17 . The three-dimensional memory device of claim 1 , further comprising:
a connection bridge disposed over the insulating layer of the separating structure and extending in the first lateral direction.
18 . The three-dimensional memory device of claim 17 , wherein the connection bridge is configured to electrically connect an array common source arranged at opposite sides of the insulating layer of the separating structure in the first lateral direction.
19 . The three-dimensional memory device of claim 18 , wherein a spacer is arranged on sidewalls of the separating structure, in a vertical direction perpendicular to the first lateral direction, between the array common source arranged at the opposite sides in the first lateral direction.
20 . A three-dimensional memory device, comprising:
a substrate;
a stacked structure arranged on the substrate and comprising gate layers and dielectric layers, wherein the gate layers and the dielectric layers are alternately stacked;
gate line slits penetrating through the stacked structure to the substrate, wherein the gate line slits are separated by a separating structure;
an insulating layer disposed on the separating structure and extending outward from the separating structure to cover the stacked structure, wherein a surface of the insulating layer on the separating structure and a surface of the insulating layer on the stacked structure, deviating away from the substrate, are flat; and
a connection bridge disposed over the insulating layer of the separating structure and extending in a first lateral direction,
wherein:
the connection bridge is configured to electrically connect an array common source arranged at opposite sides of the insulating layer of the separating structure in the first lateral direction; and
a spacer is arranged on sidewalls of the separating structure, in a vertical direction perpendicular to the first lateral direction, between the array common source arranged at the opposite sides in the first lateral direction.