Semiconductor memory device including gate electrodes with internal voids and electronic system including the same
A semiconductor memory device includes a cell substrate including a cell array region and an extended region, gate electrodes stacked on the cell substrate, the gate electrodes including molybdenum, and channel structures in the cell array region, the channel structures penetrating the gate electrodes, wherein at least one of the gate electrodes includes at least one void in a region between the channel structures.
1 . A semiconductor memory device, comprising:
a cell substrate including a cell array region and an extended region;
gate electrodes stacked on the cell substrate, the gate electrodes including molybdenum; and
channel structures in the cell array region, the channel structures penetrating the gate electrodes,
wherein;
at least one of the gate electrodes includes a plurality of voids arranged laterally in a region between a pair of laterally adjacent channel structures of the channel structures, and
each of the plurality of voids is an empty space.
2 . The semiconductor memory device as claimed in claim 1 , wherein a size of voids of the plurality of voids increases successively as a distance from the cell substrate increases.
3 . The semiconductor memory device as claimed in claim 1 , further comprising a block separation structure in the cell array region, the block separation structure penetrating the gate electrodes, and portions of the gate electrodes between the block separation structure and respective ones of the channel structures do not include any voids.
4 . The semiconductor memory device as claimed in claim 3 , wherein a size of voids of the plurality of voids increases successively as a distance from the block separation structure increases.
5 . The semiconductor memory device as claimed in claim 1 , further comprising dummy channel structures in the extended region, the dummy channel structures penetrating the gate electrodes, and portions of the gate electrodes between adjacent ones of the dummy channel structures do not include any voids.
6 . The semiconductor memory device as claimed in claim 5 , wherein a distance between adjacent ones of the dummy channel structures is greater than a distance between adjacent ones of the channel structures.
7 . The semiconductor memory device as claimed in claim 1 , wherein a width of the channel structures increases as a distance from the cell substrate increases.
8 . The semiconductor memory device as claimed in claim 1 , further comprising a string separation pattern in the cell array region, the string separation pattern penetrating only a subset of the gate electrodes wherein a portions of each gate electrodes of the subset of the gate electrodes between the string separation pattern and an adjacent one of the channel structures includes at least one void.
9 . The semiconductor memory device as claimed in claim 1 , further comprising a string separation pattern in the cell array region, the string separation pattern penetrating only a subset of the gate electrodes so that the string separation pattern is located between two voids located in one or more gate electrodes of the subset of the gate electrodes.
10 . The semiconductor memory device as claimed in claim 1 , further comprising a string separation pattern in the cell array region, the string separation pattern penetrating only some of the gate electrodes, wherein each of the some of the gate electrodes does not include any voids in a portion located between the string separation pattern and an adjacent one of the channel structures.
11 . The semiconductor memory device as claimed in claim 1 , further comprising:
a peripheral circuit board;
a wiring structure on the peripheral circuit board; and
an inter-wiring insulating film which covers the wiring structure on the peripheral circuit board, the cell substrate being stacked on the inter-wiring insulating film.
12 . The semiconductor memory device as claimed in claim 1 , further comprising a barrier layer which surrounds the gate electrodes.
13 . The semiconductor memory device as claimed in claim 1 , wherein each of the plurality of voids has a circular cross-sectional shape.
14 . A semiconductor memory device, comprising:
a cell substrate;
first gate electrodes stacked on the cell substrate, the first gate electrodes extending in a first direction and including molybdenum;
second gate electrodes stacked on the first gate electrodes, the second gate electrodes extending in the first direction and including molybdenum;
channel structures penetrating the first gate electrodes and the second gate electrodes;
block separation structures penetrating the first gate electrodes and the second gate electrodes, the block separation structures extending in the first direction and being spaced apart from each other in a second direction different from the first direction; and
a first plurality of voids inside at least one of the first gate electrodes and a second plurality of voids inside at least one of the second gate electrodes, the first plurality of voids and second plurality of voids each arranged between adjacent ones of the channel structures, each void of the first and second plurality of voids being an empty space, and
wherein a region between one of the block separation structures and an adjacent one of the channel structures of the first and second gate electrodes is free of any voids,
wherein the channel structures include first to third channel structures arranged, in a top plan view, at vertices of a triangle, and
wherein, from the top plan view, a center of one of the first plurality of voids or a center of one of the second plurality of voids is at a center of the first to third channel structures.
15 . The semiconductor memory device as claimed in claim 14 , wherein:
the first plurality of voids includes a first void in an uppermost of the first gate electrodes and a second void in a lowermost of the first gate electrodes, a size of the first void being greater than a size of the second void, and
the second plurality of voids includes a third void in an uppermost of the second gate electrodes and a fourth void in a lowermost of the second gate electrodes, a size of the third void being greater than a size of the fourth void.
16 . The semiconductor memory device as claimed in claim 14 , further comprising a string separation pattern penetrating only some of the second gate electrodes between the block separation structures, wherein a portion of each of the some of the second gate electrodes between the string separation pattern and an adjacent one of the channel structures includes at least one void.
17 . The semiconductor memory device as claimed in claim 14 , further comprising a string separation pattern penetrating only a subset of the second gate electrodes between the block separation structures, wherein a portion of each gate electrode of the subset of the second gate electrodes between the string separation pattern and an adjacent one of the channel structures includes at least one void on at least one side wall of the string separation pattern.
18 . The semiconductor memory device as claimed in claim 14 , wherein a size of voids of the first plurality of voids or voids of the second plurality of voids increase successively as a distance from the block separation structures increases.
19 . An electronic system, comprising:
a main board;
a semiconductor memory device on the main board, the semiconductor memory device including:
a first structure including a peripheral circuit,
a second structure including an I/O connection wiring electrically connected to the peripheral circuit, and
an I/O pad electrically connected to the I/O connection wiring extending into the second structure; and
a controller electrically connected to the semiconductor memory device on the main board,
wherein the second structure of the semiconductor memory device includes:
a cell substrate including a cell array region and an extended region,
gate electrodes stacked on the cell substrate, the gate electrodes including molybdenum,
channel structures in the cell array region, the channel structures penetrating the gate electrodes, and
a block separation structure that penetrates the gate electrodes, and
wherein at least one of the gate electrodes in a region between a pair of laterally adjacent channel structures of the channel structures includes a laterally arranged plurality of voids, each of the plurality of voids being an empty space, and a portion of each of the gate electrodes between the block separation structure and an adjacent one of the channel structures does not include any voids.
20 . The electronic system as claimed in claim 19 , wherein a size of voids of the plurality of voids increases successively as a distance from the cell substrate increases.