Three-dimensional memory device with support structures in gate line slits and methods for forming the same
A three-dimensional (3D) memory device includes a memory stack including interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack, a memory block including a plurality of channel structures extending vertically through the memory stack, a plurality of source structures extending vertically and laterally in the memory stack and being in contact with the memory block, and a plurality of conductor portions and a plurality of insulating portions being interleaved and locating between two adjacent source structures along a direction which the source structure extends. The interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks.
1 . A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductor layers and insulating layers extending laterally in the memory stack;
a memory block comprising a plurality of channel structures extending vertically through the memory stack;
a plurality of source structures extending vertically and laterally in the memory stack and in contact with the memory block; and
a plurality of conductor portions and a plurality of insulating portions vertically interleaved and located between two adjacent source structures along a lateral direction in which a source structure of the plurality of source structures extends, wherein a dividing structure, comprising an insulating material, is arranged between the two adjacent source structures to separate end portions of the two adjacent source structures,
wherein the plurality of conductor portions and the plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of a same level of adjacent memory blocks.
2 . The 3D memory device of claim 1 , further comprising the dividing structure, wherein the dividing structure extends vertically and is located on the plurality of conductor portions and plurality of insulating portions.
3 . The 3D memory device of claim 2 , wherein
the dividing structure extends laterally to connect the adjacent memory blocks; and
the plurality of conductor portions are insulated from the two adjacent source structures.
4 . The 3D memory device of claim 3 , wherein along another lateral direction perpendicular to the lateral direction along which the source structure extends, a width of the dividing structure is greater than or equal to a width of each of the two adjacent source structures.
5 . The 3D memory device of claim 2 , wherein the insulating material of the dividing structure comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.
6 . The 3D memory device of claim 5 , wherein
the plurality of conductor portions comprises at least one of tungsten, aluminum, copper, cobalt, silicides, or polysilicon; and
the plurality of insulating portions comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.
7 . The 3D memory device of claim 6 , wherein
the plurality of conductor portions and the conductor layers of the adjacent memory blocks comprise a same material; and
the plurality of insulating portions and the insulating layers of the adjacent memory blocks comprise a same material.
8 . The 3D memory device of claim 5 , further comprising a cut structure extending laterally and vertically in parallel with the source structure in the memory block and dividing the memory block into a plurality of memory fingers, wherein the cut structure extends vertically into an insulating layer of the memory stack and comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride, a depth of the cut structure being the same as a depth of the dividing structure.
9 . The 3D memory device of claim 1 , wherein a top surface of the dividing structure is substantially coplanar with top surfaces of the two adjacent source structures.
10 . The 3D memory device of claim 1 , wherein a width of the dividing structure, in another lateral direction perpendicular to the lateral direction, is greater than a width of each of the two adjacent source structures to separate the two adjacent source structures in the lateral direction.
11 . A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductor layers and insulating layers extending laterally in the memory stack;
a first source region comprising a first source structure extending vertically and laterally in the memory stack;
a second source region comprising a plurality of second source structures extending vertically and laterally in the memory stack; and
a plurality of conductor portions and a plurality of insulating portions vertically interleaved and located between two adjacent second source structures along a lateral direction in which a second source structure of the plurality of second source structures extends, wherein a dividing structure, comprising an insulating material, is arranged between the two adjacent second source structures to separate end portions of the two adjacent second source structures,
wherein the plurality of conductor portions are in contact with corresponding conductor layers and the plurality of insulating portions are in contact with corresponding insulating layers.
12 . The 3D memory device of claim 11 , further comprising the dividing structure, wherein the dividing structure extends vertically and is located on the plurality of conductor portions and the plurality of insulating portions.
13 . The 3D memory device of claim 12 , wherein
the plurality of conductor portions are insulated from the two adjacent second source structures.
14 . The 3D memory device of claim 13 , wherein along another lateral direction perpendicular to the lateral direction along which the second source structure extends, a width of the dividing structure is greater than or equal to a width of each of the two adjacent second source structures.
15 . The 3D memory device of claim 12 , wherein the insulating material of the dividing structure comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.
16 . The 3D memory device of claim 15 , wherein
the plurality of conductor portions comprises at least one of tungsten, aluminum, copper, cobalt, silicides, or polysilicon; and
the plurality of insulating portions comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.
17 . The 3D memory device of claim 16 , wherein
the plurality of conductor portions and the conductor layers of adjacent memory blocks comprise a same material; and
the plurality of insulating portions and the insulating layers of the adjacent memory blocks comprise a same material.
18 . The 3D memory device of claim 15 , further comprising a cut structure extending laterally and vertically between the first source structure and the second source structure or between the two adjacent second source structures, wherein the cut structure extends vertically into an insulating layer of the memory stack and comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride, a depth of the cut structure being the same as a depth of the dividing structure.
19 . The 3D memory device of claim 11 , wherein a top surface of the dividing structure is substantially coplanar with top surfaces of the two adjacent second source structures.
20 . The 3D memory device of claim 11 , wherein a width of the dividing structure, in another lateral direction perpendicular to the lateral direction, is greater than a width of each of the two adjacent second source structures to separate the two adjacent second source structures in the lateral direction.