Memory device containing TSG deck with reduced wafer bow and method of forming the same
Memory device, memory system, and formation method are provided. The formation method includes providing a dielectric-pair stack containing a channel layer extending there-through, and forming a sacrificial layer in the dielectric-pair stack and in contact with the channel layer; forming a semiconductor layer over the dielectric-pair stack, the semiconductor layer containing a top selective gate (TSG) cut structure; forming a trench through the semiconductor layer to expose the sacrificial layer; forming a barrier layer on sidewalls of the semiconductor layer exposed by the trench; forming a recess by removing the sacrificial layer; and forming a channel plug structure in the trench and the recess.
1 . A memory device comprising:
a stack structure;
a semiconductor layer over the stack structure and containing a top selective gate (TSG) cut structure;
a channel plug structure passing through the semiconductor layer, and penetrating into the stack structure and in contact with a channel layer, the channel layer extending through the stack structure;
a barrier layer through the semiconductor layer and separating the channel plug structure from the semiconductor layer along a lateral direction of the semiconductor layer; and
slit structures extending through the stack structure and laterally arranged in parallel, wherein
the TSG cut structure is in parallel with the slit structures laterally and separates a plurality of channel plug structures configured between the slit structures into groups.
2 . The memory device according to claim 1 , further comprising:
a deck structure comprising:
a dielectric layer over the stack structure, a deck cap layer, and the semiconductor layer between the dielectric layer and the deck cap layer, wherein
the channel plug structure further passes through the dielectric layer and the deck cap layer.
3 . The memory device according to claim 1 , wherein
the channel plug structure includes an upper plug portion through the semiconductor layer and a lower plug portion in the stack structure, and
at an interface between the upper and lower plug portions, the upper plug portion includes a width less than the lower plug portion.
4 . The memory device according to claim 1 , wherein
a lower plug portion of the channel plug structure is in contact with the channel layer, and
the lower plug portion includes a sidewall surrounded by the channel layer or includes a bottom surface on the channel layer.
5 . The memory device according to claim 1 , further comprising:
a channel structure extending through the stack structure and comprising a functional layer between the channel layer and the stack structure,
the functional layer comprising:
a tunneling layer adjacent to the channel layer, a blocking layer adjacent to the stack structure, and a charge trap layer between the blocking layer and the tunneling layer, wherein
a lower plug portion of the channel plug structure is formed above the channel layer and the tunneling layer, and further surrounded by the charge trap layer.
6 . The memory device according to claim 1 , wherein
the TSG cut structure is between an upper plug portion of the channel plug structure and an adjacent upper plug portion of an adjacent channel plug structure along the lateral direction of the semiconductor layer.
7 . The memory device according to claim 1 , wherein
the channel plug structure contains an airgap under the semiconductor layer.
8 . The memory device according to claim 1 , wherein
the stack structure comprises a dielectric-pair stack or a stack structure comprising alternating layers of a conductor layer and a dielectric layer.
9 . The memory device according to claim 1 , wherein
the TSG cut structure has a thickness same as the semiconductor layer along a vertical direction.
10 . The memory device according to claim 1 , wherein
the TSG cut structure separates from the stack structure by a dielectric layer over the stack structure.
11 . The memory device according to claim 1 , further comprising:
a dielectric filling material under the channel plug structure, passing through the stack structure, and surrounded by the channel layer.
12 . The memory device according to claim 1 , wherein the barrier layer has a thickness same as the semiconductor layer along a vertical direction.
13 . A method for forming the memory device according to claim 11 , comprising:
providing a dielectric-pair stack containing the channel layer extending there-through, and forming a sacrificial layer in the dielectric-pair stack and in contact with the channel layer;
forming the semiconductor layer over the dielectric-pair stack, the semiconductor layer containing the top selective gate (TSG) cut structure;
forming a trench through the semiconductor layer to expose the sacrificial layer;
forming the barrier layer on sidewalls of the semiconductor layer exposed by the trench;
forming a recess by removing the sacrificial layer; and
forming the channel plug structure in the trench and the recess.
14 . The method according to claim 13 , wherein
the channel plug structure includes an upper plug portion formed in the trench and a lower plug portion formed in the recess, and
at an interface between the upper and lower plug portions, the upper plug portion includes a width less than the lower plug portion.
15 . The method according to claim 13 , wherein
the sacrificial layer is formed in the dielectric-pair stack either having a sidewall surrounded by the channel layer or having a bottom surface over the channel layer.
16 . The method according to claim 13 , wherein forming the barrier layer comprises:
performing an oxidation process to convert a portion of the sidewalls of the semiconductor layer exposed by the trench into the barrier layer; or
depositing the barrier layer selectively on the sidewalls of the semiconductor layer exposed by the trench.
17 . The method according to claim 13 , wherein
a deck structure is formed over the dielectric-pair stack, the deck structure comprising:
a dielectric layer,
a deck cap layer; and
the semiconductor layer, the barrier layer, and the TSG cut structure, that are between the dielectric layer and the deck cap layer.
18 . The method according to claim 13 , wherein forming the channel plug structure further comprises:
forming an airgap in a portion of the channel plug structure under the semiconductor layer.
19 . The memory device according to claim 1 , wherein
the TSG cut structure is made of a material including a dielectric layer, and
the channel plug structure is made of a material comprising polysilicon.
20 . A memory system comprising:
a controller, and
a memory device comprising:
a stack structure;
a semiconductor layer over the stack structure and containing a top selective gate (TSG) cut structure;
a channel plug structure passing through the semiconductor layer, and penetrating into the stack structure and in contact with a channel layer, the channel layer extending through the stack structure;
a barrier layer through the semiconductor layer and separating the channel plug structure from the semiconductor layer along a lateral direction of the semiconductor layer; and
slit structures extending through the stack structure and laterally arranged in parallel, wherein the TSG cut structure is in parallel with the slit structures laterally and separates a plurality of channel plug structures configured between the slit structures into groups,
wherein the controller is configured to control the memory device.