Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate, data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction that intersect each other and are parallel to a top surface of the substrate, first cell conductive lines that extend in the first direction and are spaced apart from each other in the second direction on the data storage patterns, cell via contacts that are spaced apart from each other in the first direction and disposed between a pair of the first cell conductive lines, dummy data storage patterns that are spaced apart from each other in the first direction between the first cell conductive lines and are disposed between the cell via contacts, and upper conductive lines on the cell via contacts and electrically connected to the cell via contacts, respectively.
1 . A semiconductor device, comprising:
a substrate;
a plurality of data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate;
a plurality of first cell conductive lines extending in the first direction and being spaced apart from each other in the second direction on the data storage patterns, each of the plurality of first cell conductive lines being connected to a corresponding column of data storage patterns that are spaced apart from each other in the first direction among the plurality of data storage patterns;
a plurality of cell via contacts spaced apart from each other in the first direction and disposed between a pair of the plurality of first cell conductive lines;
a plurality of dummy data storage patterns spaced apart from each other in the first direction and disposed between the pair of the plurality of first cell conductive lines, the plurality of dummy data storage patterns being interposed between the plurality of cell via contacts; and
a plurality of upper conductive lines on the plurality of cell via contacts and electrically connected to the plurality of cell via contacts, respectively.
2 . The semiconductor device of claim 1 , wherein the plurality of cell via contacts and the plurality of dummy data storage patterns are alternately disposed along the first direction between the pair of the plurality of first cell conductive lines.
3 . The semiconductor device of claim 1 , further comprising:
a plurality of first conductive contacts on the plurality of cell via contacts, respectively, wherein
each of the plurality of upper conductive lines is electrically connected through a corresponding one of the plurality of first conductive contacts to a corresponding one of the plurality of cell via contacts.
4 . The semiconductor device of claim 1 , wherein
top surfaces of the plurality of cell via contacts are at same heights as top surfaces of the plurality of first cell conductive lines.
5 . The semiconductor device of claim 1 , wherein a material of the plurality of cell via contacts is same as a material of the plurality of the first cell conductive lines.
6 . The semiconductor device of claim 1 , wherein the plurality of dummy data storage patterns are offset in the first direction from the corresponding column of data storage patterns.
7 . The semiconductor device of claim 6 , wherein the plurality of cell via contacts are aligned in the second direction with a corresponding row of data storage patterns that are arranged in the second direction among the plurality of data storage patterns.
8 . The semiconductor device of claim 1 , wherein the plurality of cell via contacts are offset in the first direction from the corresponding column of data storage patterns.
9 . The semiconductor device of claim 8 , wherein each of the plurality of dummy storage patterns is aligned in the second direction with a corresponding row of data storage patterns that are arranged in the second direction among the plurality of data storage patterns.
10 . The semiconductor device of claim 9 , wherein
the corresponding column data storage patterns are spaced apart from each other at a first pitch along the first direction,
the plurality of cell via contacts and the plurality of dummy data storage pattern are spaced apart from each other at a second pitch along the first direction, and
the second pitch is less than the first pitch.
11 . The semiconductor device of claim 10 , wherein the second pitch is half the first pitch.
12 . The semiconductor device of claim 1 , further comprising:
a wiring structure between the substrate and the plurality of data storage patterns; and
a plurality of lower electrode contacts between the wiring structure and the plurality of data storage patterns, wherein
the plurality of lower electrode contacts are connected to corresponding data storage patterns among the plurality of data storage patterns,
the plurality of lower electrode contacts are connected to corresponding uppermost conductive lines among uppermost conductive lines of the wiring structure, respectively, and
the plurality of cell via contacts are connected to other corresponding uppermost conductive lines among the uppermost conductive lines of the wiring structure.
13 . The semiconductor device of claim 12 , further comprising:
a wiring dielectric layer on the substrate and covering the wiring structure;
a first lower dielectric layer on the wiring dielectric layer; and
a second lower dielectric layer on the first lower dielectric layer and covering the plurality of lower electrode contacts, wherein
the plurality of data storage patterns are on the second lower dielectric layer,
the plurality of lower electrode contacts penetrate the second lower dielectric layer and the first lower dielectric layer to connect with the corresponding uppermost conductive lines of the wiring structure,
the second lower dielectric layer has a recessed part between the plurality of data storage patterns, and
a height of a lowermost surface of the recessed part of the second lower dielectric layer is lower than a height of top surfaces the plurality of lower electrode contacts.
14 . The semiconductor device of claim 13 , wherein
the substrate includes a cell region and a peripheral region,
the plurality of lower electrode contacts, the plurality of data storage patterns, the plurality of first cell conductive lines, the plurality of dummy data storage patterns, and the plurality of upper conductive lines are on the cell region,
the wiring dielectric layer, the first lower dielectric layer, and the second lower dielectric layer cover the cell region and the peripheral region, and
a top surface of the second lower dielectric layer on the peripheral region is lower than a the lowermost surface of the recessed part of the second lower interlayer dielectric layer.
15 . The semiconductor device of claim 13 , further comprising:
a cell dielectric layer on the lower dielectric layer, wherein
the cell dielectric layer covers the plurality of data storage patterns and the plurality of dummy data storage patterns, and
the plurality of cell via contacts penetrate the cell dielectric layer and connect to the other corresponding uppermost conductive lines of the wiring structure.
16 . The semiconductor device of claim 1 , further comprising:
a plurality of second cell conductive lines extending in the first direction and spaced apart from each other in the second direction on the plurality of first cell conductive lines; and
a plurality of first conductive contacts between the plurality of first cell conductive lines and the plurality of second cell conductive lines, wherein
the plurality of second cell conductive lines are correspondingly electrically connected through the plurality of first conductive contacts to the plurality of first cell conductive lines.
17 . The semiconductor device of claim 16 , wherein heights of the plurality of upper conductive lines are higher than heights of the plurality of second cell conductive lines over the substrate.
18 . A semiconductor device, comprising:
a substrate;
a plurality of data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate;
a plurality of first cell conductive lines extending in the first direction and being spaced apart from each other in the second direction on the data storage patterns, each of the plurality of first cell conductive lines being connected to a corresponding column of data storage patterns that are spaced apart from each other in the first direction among the data storage patterns;
a plurality of cell via contacts spaced apart from each other in the first direction and disposed between a pair of the plurality of first cell conductive lines, the plurality of cell via contacts being aligned in the second direction with the corresponding column of data storage patterns; and
a plurality of dummy data storage patterns spaced apart from each other in the first direction and disposed between the pair of the plurality of first cell conductive lines, the plurality of dummy data storage patterns being disposed between the plurality of cell via contacts.
19 . The semiconductor device of claim 18 , further comprising:
a plurality of first conductive contacts on the plurality of cell via contacts, respectively; and
a plurality of upper conductive lines on and correspondingly connected to the plurality of first conductive contacts,
wherein the plurality of upper conductive lines are electrically connected to the plurality of cell via contacts through the plurality of first conductive contacts, respectively.
20 . The semiconductor device of claim 18 , wherein the plurality of dummy data storage patterns are offset in the first direction from the corresponding column of data storage patterns.