Semiconductor device

1 . A semiconductor device comprising:

a bit line;

a first barrier layer disposed on the bit line;

a variable resistance layer disposed on the first barrier layer;

a second barrier layer disposed on the variable resistance layer; and

a word line disposed on the second barrier layer, being in contact with the second barrier layer, and spaced apart from the variable resistance layer,

wherein the second barrier layer is disposed between the variable resistance layer and the word line, and

wherein a dielectric constant of the second barrier layer is greater than a dielectric constant of the first barrier layer.

2 . The semiconductor device of claim 1 , wherein a thickness of the second barrier layer is thicker than a thickness of the first barrier layer.

3 . The semiconductor device of claim 1 , wherein the variable resistance layer comprises a trap site in which electrons introduced from the bit line are captured, and

wherein the variable resistance layer has an electrical resistance changed according to an amount of electrons captured in the trap site.

4 . The semiconductor device of claim 1 , wherein the second barrier layer includes ferroelectrics.

5 . The semiconductor device of claim 1 , wherein the variable resistance layer includes a metal oxide, and

wherein the metal oxide includes at least one of hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, and tungsten oxide.

6 . The semiconductor device of claim 1 , wherein the first barrier layer, the variable resistance layer, and the second barrier layer form a pillar structure between the bit line and the word line.

7 . The semiconductor device of claim 1 , wherein the bit line and the word line extend in different directions.

8 . A semiconductor device comprising:

a bit line extending in a first direction;

a word line extending in a second direction perpendicular to the first direction; and

a memory cell having a pillar structure, which is disposed in a region in which the bit line and the word line overlap with each other,

wherein the memory cell includes a first barrier layer adjacent to the bit line, a second barrier layer adjacent to the word line, and a variable resistance layer between the first barrier layer and the second barrier layer,

wherein the second barrier layer is disposed between the variable resistance layer and the word line,

wherein a dielectric constant of the second barrier layer is greater than a dielectric constant of the first barrier layer, and

wherein a thickness of the second barrier layer is greater than a thickness of the first barrier layer.

9 . The semiconductor device of claim 8 , wherein the variable resistance layer comprises a trap site in which electrons introduced from the bit line are captured, and

wherein the variable resistance layer has an electrical resistance changed according to an amount of electrons captured in the trap site.

10 . The semiconductor device of claim 8 , wherein the variable resistance layer includes a metal oxide, and

wherein the metal oxide includes at least one of hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, and tungsten oxide.

11 . A semiconductor device comprising:

a first bit line extending in a first direction;

a first memory cell overlapping with a portion of a top surface of the first bit line;

a word line extending in a second direction perpendicular to the first direction on the first memory cell;

a second memory cell overlapping with a portion of a top surface of the word line; and

a second bit line extending in the first direction on the second memory cell,

wherein the first memory cell includes a first barrier layer, a second barrier layer, and a first variable resistance layer disposed between the first and the second barrier layers,

wherein the second memory cell includes a third barrier layer, a fourth barrier layer, and a second variable resistance layer disposed between the third and the fourth barrier layers,

wherein the second barrier layer and the third barrier layer include ferroelectrics, and

wherein the first variable resistance layer and the second variable resistance layer include a transition metal oxide.

12 . The semiconductor device of claim 11 , wherein the first barrier layer is disposed between the first bit line and the first variable resistance layer,

wherein the second barrier layer is disposed between the first variable resistance layer and the word line,

wherein the third barrier layer is disposed between the word line and the second variable resistance layer, and

wherein the fourth barrier layer is disposed between the second variable resistance layer and the second bit line.

13 . The semiconductor device of claim 11 , wherein the first memory cell and the second memory cell have a pillar structure.

14 . The semiconductor device of claim 11 , wherein a thickness of the second barrier layer is greater than a thickness of the first barrier layer, and

a thickness of the third barrier layer is greater than a thickness of the fourth barrier layer.

15 . The semiconductor device of claim 11 , wherein a dielectric constant of the second barrier layer is greater than a dielectric constant of the first barrier layer, and

a dielectric constant of the third barrier layer is greater than a dielectric constant of the fourth barrier layer.

16 . The semiconductor device of claim 11 , wherein the first variable resistance layer and the second variable resistance layer include a metal oxide which does not satisfy a stoichiometric ratio.