Semiconductor device having reduced risk of dielectric breakdown
Provided is a semiconductor device including a semiconductor substrate. The semiconductor substrate has: an active portion; and a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction. The semiconductor device further includes: a gate runner provided between the active portion and an end side of the semiconductor substrate; and a plurality of gate polysilicon disposed apart from each other along the end side and respectively connecting the plurality of gate trench portions to the gate runner.
1 . A semiconductor device comprising a semiconductor substrate, wherein
the semiconductor substrate has:
an active portion;
a circumferential well region surrounding the active portion;
a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction; and
a plurality of dummy trench portions provided in the active portion on the upper surface of the semiconductor substrate and extending along the extending direction, the semiconductor device further comprising:
a gate runner provided between the active portion and an end side of the semiconductor substrate, the gate runner having a portion extending in a direction perpendicular to the extending direction in top view; and
a plurality of gate polysilicon disposed apart from each other and distributed along the portion of the gate runner extending in the direction perpendicular to the extending direction in top view and each of the plurality of gate polysilicon connecting one or more corresponding gate trench portions of the plurality of gate trench portions to the gate runner, wherein
a distance in the extending direction from each of the plurality of dummy trench portions to the portion of the gate runner extending in the direction perpendicular to the extending direction in top view is longer than a distance in the extending direction from each of the plurality of gate trench portions to the portion of the gate runner extending in the direction perpendicular to the extending direction in top view,
each of the plurality of gate polysilicon has a lower surface, and
in a depth direction of the semiconductor substrate, a lower surface of the gate runner is farther from the upper surface of the semiconductor substrate than the lower surface of each of the plurality of gate polysilicon.
2 . The semiconductor device according to claim 1 , wherein
at least one of the gate trench portions has:
two linear portions extending along the extending direction; and
an edge portion connecting the two linear portions, and
a width of the gate trench portion including the two linear portions in an array direction perpendicular to the extending direction is larger than a width of the gate polysilicon connected to the gate trench portion in the array direction.
3 . The semiconductor device according to claim 1 , wherein
at least one of the gate trench portions has one linear portion extending along the extending direction, and
a width of the gate trench portion in an array direction perpendicular to the extending direction is larger than a width of the gate polysilicon connected to the gate trench portion in the array direction.
4 . The semiconductor device according to claim 1 , wherein
the semiconductor substrate has:
two first end sides perpendicular to the extending direction; and
two second end sides parallel to the extending direction,
the gate runner has:
a first wiring provided between the first end side and the active portion; and
a second wiring provided between the second end side and the active portion, and
the gate polysilicon is
provided below the first wiring, and
not provided below the second wiring.
5 . The semiconductor device according to claim 1 , wherein
the gate polysilicon has a long side in a direction from the gate runner toward the gate trench portion.
6 . The semiconductor device according to claim 5 , wherein
the gate polysilicon has a long side in the extending direction.
7 . The semiconductor device according to claim 1 , wherein
at least a part of each of the plurality of gate trench portions is provided to extend to a location below the lower surface of the gate runner, and
each of the plurality of gate polysilicon is provided between its corresponding one or more of the plurality of gate trench portions and the gate runner in a depth direction.
8 . The semiconductor device according to claim 1 , wherein
the gate runner further comprises at least one curved portion extending from an end of the portion of the gate runner extending in the direction perpendicular to the extending direction in top view,
the plurality of gate polysilicon are distributed along the curved portion of the gate runner and the portion of the gate runner extending in the direction perpendicular to the extending direction in top view,
angles formed by longitudinal directions of at least two gate polysilicon of the plurality of gate polysilicon with the extending direction are different from each other, and
the angle formed with the extending direction and an angle formed with the direction perpendicular to the extending direction in top view by at least one of the two gate polysilicon are both greater than zero.
9 . The semiconductor device according to claim 8 , wherein
the semiconductor substrate has:
two first end sides perpendicular to the extending direction; and
two second end sides parallel to the extending direction,
the gate runner comprises:
a first wiring provided between the first end side and the active portion;
a second wiring provided between the second end side and the active portion; and
a curved portion connecting the first wiring and the second wiring, and
a longitudinal direction of the gate polysilicon connected to the first wiring is different from a longitudinal direction of the gate polysilicon connected to the curved portion.
10 . The semiconductor device according to claim 1 , wherein
the semiconductor substrate has:
two first end sides perpendicular to the extending direction; and
two second end sides parallel to the extending direction,
the gate runner comprises:
a first wiring provided between the first end side and the active portion;
a second wiring provided between the second end side and the active portion; and
a curved portion connecting the first wiring and the second wiring,
at least a part of the gate trench portion is provided to extend to a lower side of the curved portion of the gate runner,
at least one of the gate polysilicon is provided between the gate trench portion and the curved portion in a depth direction, and
at least one of the gate polysilicon has a long side in a direction from the first wiring of the gate runner toward the gate trench portion.
11 . The semiconductor device according to claim 2 , wherein
the semiconductor substrate has:
two first end sides perpendicular to the extending direction; and
two second end sides parallel to the extending direction,
the gate runner has:
a first wiring provided between the first end side and the active portion; and
a second wiring provided between the second end side and the active portion, and
the gate polysilicon is
provided below the first wiring, and
not provided below the second wiring.
12 . The semiconductor device according to claim 3 , wherein
the semiconductor substrate has:
two first end sides perpendicular to the extending direction; and
two second end sides parallel to the extending direction, the gate runner has:
a first wiring provided between the first end side and the active portion; and
a second wiring provided between the second end side and the active portion, and
the gate polysilicon is
provided below the first wiring, and
not provided below the second wiring.
13 . The semiconductor device according to claim 2 , wherein
the gate polysilicon has a long side in a direction from the gate runner toward the gate trench portion.
14 . The semiconductor device according to claim 3 , wherein
the gate polysilicon has a long side in a direction from the gate runner toward the gate trench portion.
15 . The semiconductor device according to claim 7 , wherein a portion of each of the plurality of gate trench portions is overlapped by the portion of the gate runner extending in the direction perpendicular to the extending direction in top view.
16 . The semiconductor device according to claim 1 , wherein a portion of each of the plurality of gate trench portions is overlapped by the portion of the gate runner extending in the direction perpendicular to the extending direction in top view.
17 . A semiconductor device comprising a semiconductor substrate, wherein
the semiconductor substrate has:
an active portion; and
a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction, the semiconductor device further comprising:
a gate runner provided between the active portion and an end side of the semiconductor substrate, the gate runner having a portion extending in a direction perpendicular to the extending direction in top view; and
a plurality of gate polysilicon disposed apart from each other and distributed along the portion of the gate runner extending in the direction perpendicular to the extending direction in top view and each of the plurality of gate polysilicon connecting one or more corresponding gate trench portions of the plurality of gate trench portions to the gate runner, wherein
each of the plurality of gate polysilicon has a lower surface, in a depth direction of the semiconductor substrate, a lower surface of the gate runner is farther from the upper surface of the semiconductor substrate than the lower surface of each of the plurality of gate polysilicon,
at least one gate trench portion of the plurality of gate trench portions has one linear portion extending along the extending direction, and
a width of the linear portion of the at least one gate trench portion in an array direction perpendicular to the extending direction is larger than a width, in the array direction, of a corresponding gate polysilicon of the plurality of gate polysilicon that is connected to the at least one gate trench portion.