Semiconductor device
This semiconductor device includes: an n-type drift layer; a p-type base region; a trench extending in the depth direction so as to pass through the base region and reach the drift layer; an insulating film formed on an inner surface of the trench; a gate trench surrounding the insulating film; and a p-type column region provided on the drift layer at a position at the bottom of the trench. The drift layer includes: a first region having a first concentration peak; and a second region that is provided at a position deeper than the trench and corresponding to the column region, and has a second concentration peak lower than the first concentration peak.
1 . A semiconductor device, comprising:
a drift layer of a first conductive type;
a body region of a second conductive type formed in the drift region at a side closer to a top surface of the drift region;
a trench extending in a depth direction through the body region to the drift layer;
an insulation film formed on a wall surface of the trench;
a gate electrode surrounded by the insulation film; and
a column region of a second conductive type located at a bottom portion of the trench in the drift layer;
the drift layer including:
a first region having a first concentration peak; and
a second region located at a position deeper than the trench and corresponding to the column region, the second region having a second concentration peak that is lower than the first concentration peak, wherein the first region and the second region are separated from one another in the depth direction.
2 . The semiconductor device according to claim 1 , wherein:
the trench includes multiple trenches arranged so as to be separated from each other; and
the column region includes multiple column regions provided in correspondence with the multiple trenches.
3 . The semiconductor device according to claim 2 , wherein:
the first region is located between adjacent ones of the trenches in an arrangement direction of the trenches; and
the second region is located between adjacent ones of the column regions in the arrangement direction of the trenches.
4 . The semiconductor device according to claim 3 , wherein the first region is located in the drift region proximate to an interface between the drift region and the body region.
5 . The semiconductor device according to claim 3 , wherein the second region includes a portion located at a position same as the position corresponding to the column region in the depth direction of the trench.
6 . The semiconductor device according to claim 3 , wherein the second region includes a portion located at a position separated from the position corresponding to the column region in the depth direction of the trench.
7 . The semiconductor device according to claim 2 , wherein adjacent ones of the trenches in an arrangement direction of the trenches are spaced apart by a distance that is less than or equal to width of each of the trenches.
8 . The semiconductor device according to claim 1 , wherein the column region entirely covers the bottom portion of the trench.
9 . The semiconductor device according to claim 1 , wherein the column region is located at a position separated from the body region in a depth direction of the drift layer.
10 . The semiconductor device according to claim 9 , wherein the column region is in an electrically floating state.
11 . The semiconductor device according to claim 1 , wherein the column region is connected to the body region.
12 . The semiconductor device according to claim 1 , wherein the column region has an impurity concentration that is less than that of the body region.
13 . The semiconductor device according to claim 1 , wherein the column region has an impurity concentration with a maximum value that is higher than the second concentration peak.
14 . The semiconductor device according to claim 1 , wherein the column region has an impurity concentration with a maximum value that is higher than the first concentration peak.
15 . The semiconductor device according to claim 1 , wherein:
the drift layer includes a third region located at a deeper position than the second region; and
the second concentration peak is higher than an impurity concentration of the third region.
16 . The semiconductor device according to claim 1 , further comprising:
a main cell region, forming an IGBT, and a diode cell region, forming a freewheeling diode connected to the IGBT;
the trench being formed in both of the main cell region and the diode cell region; and
the column region being located at the bottom portion of the trench formed in the main cell region, and at the bottom portion of the trench formed in the diode cell region.
17 . The semiconductor device according to claim 1 , further comprising:
a main cell region that forms an IGBT and a diode cell region that forms a freewheeling diode connected to the IGBT;
the trench being formed in both of the main cell region and the diode cell region; and
the column region trench being located selectively at the bottom portion of the trench formed in the diode cell region and not located at the bottom portion of the trench formed in the main cell region.
18 . The semiconductor device according to claim 1 , wherein:
the second region includes multiple second regions arranged so as to be separated from each other in a direction perpendicular to the depth direction.
19 . The semiconductor device according to claim 2 , wherein:
the second region includes multiple second regions arranged so as to be separated from each other in an arrangement direction of the trenches.