Carrier structure for etch-back silicon-on-insulator process
Some implementations herein describe a carrier structure and techniques of forming a semiconductor device using the carrier structure. The carrier structure includes a core layer formed from a layer of a high bandgap material, a backside layer stack formed on a backside surface of the layer of the high bandgap material, and a frontside layer stack formed on a frontside surface of the layer of the high bandgap material. The backside layer stack includes a backside chucking layer (e.g., a layer of a polysilicon material) that intervenes between a backside diffusion barrier layer and a backside adhesion layer. The frontside layer stack includes a corresponding frontside diffusion barrier layer that interfaces directly with a corresponding frontside adhesion layer. A corresponding frontside chucking layer has been eliminated. By eliminating the frontside chucking layer, a likelihood of thermally-induced stresses and/or strains due to a coefficient of thermal expansion mismatch between layers of the frontside layer stack and other layers of the semiconductor device, during formation of the semiconductor device, is reduced.
1 . A method, comprising:
forming a frontside diffusion barrier layer and a backside diffusion barrier layer over a core layer;
forming a frontside chucking layer over the frontside diffusion barrier layer and a backside chucking layer over the backside diffusion barrier layer;
removing the frontside chucking layer;
forming a frontside adhesion layer over the frontside diffusion barrier layer and a backside adhesion layer over the backside chucking layer; and
joining the frontside adhesion layer and a layer stack that includes a seed layer.
2 . The method of claim 1 ,
wherein forming the frontside chucking layer over the frontside diffusion barrier layer and the backside chucking layer over the backside diffusion barrier layer comprises:
forming the frontside chucking layer and the backside chucking layer to each have a thickness that is included in a range of 400 Angstroms to 480 Angstroms.
3 . The method of claim 1 ,
wherein forming the frontside chucking layer over the frontside diffusion barrier layer and the backside chucking layer over the backside diffusion barrier layer comprises:
concurrently forming the frontside chucking layer and the backside chucking layer from a dielectric material.
4 . The method of claim 3 ,
wherein concurrently forming the frontside chucking layer and the backside chucking layer from the dielectric material comprises:
concurrently forming the frontside chucking layer and the backside chucking layer from a p(+) type of polysilicon material.
5 . The method of claim 1 , further comprising:
forming a substrate layer of a semiconductor device over the seed layer and over the frontside adhesion layer that is formed over the frontside diffusion barrier layer.
6 . The method of claim 5 ,
wherein forming the substrate layer over the seed layer and over the frontside adhesion layer that is formed over the frontside diffusion barrier layer comprises:
forming the substrate layer through epitaxial growth of a material.
7 . A method, comprising:
forming a core layer,
wherein the core layer comprises a first material having a first coefficient of thermal expansion for a temperature range related to a growth of an epitaxial material;
forming a first adhesion layer over the core layer;
forming a diffusion barrier layer over the first adhesion layer;
forming a chucking layer over the diffusion barrier layer;
removing the chucking layer;
forming a second adhesion layer over the diffusion barrier layer; and
joining the second adhesion layer with a layer stack that includes a substrate layer that is over a seed layer,
wherein the substrate layer includes a second material having a second coefficient of thermal expansion for the temperature range related to the growth of the epitaxial material,
wherein a ratio of the second coefficient of thermal expansion to the first coefficient of thermal expansion is approximately 1:1, and
wherein joining the second adhesion layer with the layer stack includes joining the seed layer with the second adhesion layer above the diffusion barrier layer.
8 . The method of claim 7 ,
wherein the first material and the second material are a same material.
9 . The method of claim 7 ,
wherein the first material and the second material are different metal nitride materials.
10 . The method of claim 7 ,
wherein the first material comprises:
an aluminum nitride material.
11 . The method of claim 7 ,
wherein the second material comprises:
a gallium nitride material.
12 . The method of claim 7 ,
wherein the substrate layer is above an interface region between the diffusion barrier layer and the second adhesion layer.
13 . The method of claim 7 ,
wherein the first coefficient of thermal expansion is included in a range of 5.5 microns per meter Kelvin to 6.5 microns per meter Kelvin.
14 . The method of claim 7 ,
wherein the seed layer comprises:
a p(−) type of silicon material.
15 . A method comprising:
forming a first dielectric layer over a core layer;
forming a second dielectric layer over the first dielectric layer,
wherein the second dielectric layer comprises a different dielectric material from the first dielectric layer;
forming a chucking layer over the second dielectric layer;
removing the chucking layer;
forming a third dielectric layer over the second dielectric layer,
wherein the third dielectric layer comprises a same dielectric material as the first dielectric layer; and
bonding the third dielectric layer with a layer stack that includes a substrate layer that is over a seed layer,
wherein the substrate layer includes a material having a coefficient thermal of expansion approximately equal to a coefficient thermal of expansion of the core layer.
16 . The method of claim 15 ,
wherein bonding the third dielectric layer with a layer stack includes bonding the seed layer with the third dielectric layer.
17 . The method of claim 15 , wherein the seed layer comprises:
a p(−) type of silicon material.
18 . The method of claim 15 , wherein the core layer comprises aluminum nitride.
19 . The method of claim 15 , wherein the substrate layer comprises gallium nitride.
20 . The method of claim 15 , further comprising forming a high electron mobility transistor structure above the substrate layer.