LDMOS transistor device and method for forming the same

1 . A method for forming a lateral diffusion metal-oxide- semiconductor (LDMOS) transistor device, comprising:

receiving a substrate having a first region and a second region separated from each other;

forming a first implanted region in the second region;

forming a second implanted region in the second region, wherein an area of the second implanted region is less than an area of the first implanted region;

performing a first thermal operation to form a well region in the second region;

performing a second thermal operation to form a first dielectric layer in the first region, a second dielectric layer in the second region, and a third dielectric layer in the second region;

forming a first gate electrode in the first region, and a second gate electrode and a field plate in the second region; and

forming a source region and a drain region in the substrate in the second region after the forming of the second gate electrode,

wherein a thickness of the third dielectric layer is greater than a thickness of the first dielectric layer, and greater than a thickness of the second dielectric layer,

wherein a sidewall of the field plate is aligned with a sidewall of the third dielectric layer.

2 . The method of claim 1 , wherein the second implanted region is formed after the forming of the first implanted region.

3 . The method of claim 2 , wherein the first thermal operation is performed between the forming of the first implanted region and the forming of the second implanted region.

4 . The method of claim 2 , wherein the first thermal operation is performed after the forming of the second implanted region.

5 . The method of claim 1 , wherein the substrate comprises dopants of a first conductivity type, and the well region comprises dopants of a second conductivity type complementary to the first conductivity type.

6 . The method of claim 1 , wherein the second implanted region comprises arsenic (As), germanium (Ge), silicon (Si) or inert ions.

7 . The method of claim 1 , wherein the forming of the second implanted region further comprises:

forming a patterned photoresist layer over the substrate, wherein the patterned photoresist layer comprises an opening exposing a portion of the second region;

performing an ion implantation to form the second implanted region through the opening; and

removing the patterned photoresist layer.

8 . The method of claim 1 , wherein the field plate is coupled to the second gate electrode.

9 . The method of claim 1 , further comprising:

forming a sacrificial layer over the substrate prior to the forming the first implanted region; and

removing the sacrificial layer prior to the second thermal operation.

10 . A method for forming an LDMOS transistor device, comprising:

receiving a substrate of a first conductivity type;

performing a first ion implantation on the substrate, wherein the first ion implantation comprises ions of a second conductivity type complementary to the first conductivity type;

performing a second ion implantation on the substrate after the first ion implantation;

performing a first thermal operation to form a well region in the substrate;

performing a second thermal operation to simultaneously form a first dielectric layer and a second dielectric layer over the substrate, wherein a thickness of the first dielectric layer is less than a thickness of the second dielectric layer; and

forming a gate electrode over the first dielectric layer and a field plate over the second dielectric layer,

wherein a sidewall of the field plate is aligned with a sidewall of the second dielectric layer.

11 . The method of claim 10 , wherein the first thermal operation is performed between the first ion implantation and the second ion implantation, or after the second ion implantation.

12 . The method of claim 10 , wherein the second ion implantation comprises As, Ge, Si, or inert ions.

13 . The method of claim 10 , further comprising:

forming a sacrificial layer prior to the first ion implantation; and

removing the sacrificial layer prior to the second thermal operation.

14 . The method of claim 10 , further comprising forming a source region and a drain region in the substrate.

15 . The method of claim 14 , wherein the drain region is adjacent to the second dielectric layer.

16 . An LDMOS transistor device, comprising:

a stepped isolation structure disposed over a substrate, wherein the stepped isolation structure comprises:

a first portion having a first thickness;

a second portion having a second thickness greater than the first thickness; and

a third portion having a third thickness greater than the first thickness and less than the second thickness,

a gate electrode disposed over the first portion of the stepped isolation structure;

a source region disposed in the substrate;

a drain region disposed in the substrate and adjacent to the stepped isolation structure; and

a spacer disposed over the third portion of the stepped isolation structure,

wherein the second portion comprises dopants.

17 . The LDMOS transistor device of claim 16 , wherein the dopants in the second portion of the stepped isolation structure comprise As, Ge, Si or inert ions.

18 . The LDMOS transistor device of claim 16 , where a top surface of the second portion is misaligned with a top surface of the first portion, and a bottom surface of the second portion is misaligned with a bottom surface of the first portion.

19 . The LDMOS transistor device of claim 18 , wherein the top surface of the second portion is higher than a top surface of the substrate.

20 . The LDMOS transistor device of claim 16 , further comprising an isolation structure disposed in the substrate, wherein a top surface of the isolation structure is aligned with a top surface of the substrate or between a top surface of the second portion and a bottom surface of the second portion.