Semiconductor device and method of fabricating the same
A semiconductor device includes a first transistor. The first transistor includes a source region, a drain region, a semiconductive material layer, a gate dielectric film stack and a gate electrode. The semiconductive material layer is disposed between the source region and the drain region. The gate dielectric film stack is disposed on the semiconductive material layer and includes a first film layer, a second film layer and an intermediate film layer. The first film layer and the second film layer include hafnium. The intermediate layer is sandwiched in between the first film layer and the second film layer and includes hafnium, wherein a hafnium content of the intermediate film layer is lower than a hafnium content of the first film layer and a hafnium content of the second film layer. The gate electrode is disposed on the gate dielectric film stack.
1 . A semiconductor device, comprising:
a first transistor, comprising:
a source region and a drain region;
a semiconductive material layer disposed between the source region and the drain region;
a gate dielectric film stack disposed on the semiconductive material layer and comprising:
a first film layer comprising hafnium and having a thickness of T 1 , wherein the first film layer is directly contacting the semiconductive material layer;
a second film layer comprising hafnium and having a thickness of T 2 ; and
an intermediate film layer sandwiched in between the first film layer and the second film layer and comprising hafnium, and having a thickness of T 3 , wherein a hafnium content of the intermediate film layer is lower than a hafnium content of the first film layer and a hafnium content of the second film layer, and wherein a ratio of the thickness T 3 to the thickness T 1 is in a range of 5:1 to 20:1, and a ratio of the thickness T 3 to the thickness T 2 is in a range of 5:1 to 20:1; and
a gate electrode disposed on the gate dielectric film stack, and directly contacting the second film layer.
2 . The semiconductor device according to claim 1 , wherein the first film layer and the second film layer comprises Hf X Zr (1-X) O 2 , and wherein X is in a range of 0.5 to 0.7.
3 . The semiconductor device according to claim 1 , wherein the intermediate film layer comprises Hf Y Zr (1-Y) O 2 , and wherein Y is in a range of 0.3 to 0.5.
4 . The semiconductor device according to claim 1 , wherein the first film layer and the second film layer comprises Hf X Zr (1-X) O 2 , and wherein X is in a range of 0.7 to 1, and the intermediate film layer comprises Hf Y Zr (1-Y) O 2 , and wherein Y is in a range of 0.5 to 0.7.
5 . The semiconductor device according to claim 1 , wherein the intermediate film layer comprises a first sub-layer in contact with the first film layer and a second sub-layer in contact with the second film layer, and wherein an antiferroelectric induction layer is sandwiched between the first sub-layer and the second sub-layer.
6 . The semiconductor device according to claim 5 , wherein a thickness of the antiferroelectric induction layer is in a range of 1 angstrom to 5 angstroms.
7 . The semiconductor device according to claim 5 , wherein the antiferroelectric induction layer includes a material selected from the group consisting of Al 2 O 3 , La 2 O 3 , Y 2 O 3 , SiO 2 , TiO 2 and CeO 2 .
8 . The semiconductor device according to claim 1 , further comprising auxiliary antiferroelectric induction layers located in between the first film layer and the intermediate film layer, and located in between the second film layer and the intermediate film layer.
9 . The semiconductor device according to claim 1 , wherein sidewalls of the gate electrode are aligned with sidewalls of the first film layer, aligned with sidewalls of the second film layer, and aligned with sidewalls of the intermediate film layer.
10 . The semiconductor device according to claim 1 , further comprising:
a source via connected to the source region;
a drain via connected to the drain region, wherein the first film layer, the second film layer and the intermediate film layer are located in between the source via and the drain via; and
a dielectric layer laterally surrounding the source via, the drain via, the gate dielectric film stack and the gate electrode.
11 . A semiconductor device, comprising:
a substrate;
an interconnection layer disposed on the substrate, wherein the interconnection layer comprises a plurality of dielectric layers and a plurality of conductive layers alternately stacked up along a build-up direction;
a transistor array located in between the plurality of dielectric layers, wherein the transistor array comprises a first transistor, and the first transistor comprises:
a semiconductive material layer;
a source region and a drain region located on two sides of the semiconductor material layer;
a gate dielectric film stack and a gate electrode sequentially stacked over the semiconductive material layer along the build-up direction, wherein the gate dielectric film stack comprises a plurality of hafnium-based layers, and a hafnium content of the plurality of hafnium-based layers increases from a center of the gate dielectric film stack to top and bottom surfaces of the gate dielectric film stack, and the plurality of hafnium-based layers comprises a first film layer, an intermediate film layer and a second film layer stacked up in sequence along the build-up direction, and the hafnium content of the intermediate layer is lower than the hafnium content of the first film layer and the hafnium content of the second film layer, wherein the first film layer and the second film layer comprises Hf X Zr (1-X) O 2 , and wherein X is in a range of 0.7 to 1, and the intermediate film layer comprises Hf Y Zr (1-Y) O 2 , and wherein Y is in a range of 0.5 to 0.7; and
conductive terminals disposed on and electrically connected to the interconnection layer.
12 . The semiconductor device according to claim 11 , wherein the intermediate film layer comprises a first sub-layer in contact with the first film layer and a second sub-layer in contact with the second film layer, and wherein an antiferroelectric induction layer is sandwiched between the first sub-layer and the second sub-layer.
13 . The semiconductor device according to claim 9 , wherein a thickness of the first film layer and a thickness the second film layer are in a range of 1 nm to 5 nm, and a thickness of the intermediate film layer is in a range of 5 nm to 20 nm, and the thickness of the intermediate film layer is greater than the thickness of the first film layer and the thickness of the second film layer.
14 . The semiconductor device according to claim 9 , wherein the transistor array further comprises a second transistor, wherein the second transistor comprises:
a second semiconductive material layer;
a second source region and a second drain region located on two sides of the second semiconductor material layer;
a second gate dielectric film stack and a second gate electrode sequentially stacked over the second semiconductive material layer along the build-up direction, wherein the second gate dielectric film comprises two hafnium-rich HfZrO 2 layers, and a zirconium-rich HfZrO 2 layer sandwiched between the two hafnium-rich HfZrO 2 layers.
15 . The semiconductor device according to claim 11 , further comprising: a first auxiliary antiferroelectric induction layer located in between the first film layer and the intermediate film layer, wherein the first auxiliary antiferroelectric induction layer is directly contacting the first film layer and the intermediate film layer; a second auxiliary antiferroelectric induction layer located in between the second film layer and the intermediate film layer, wherein the second auxiliary antiferroelectric induction layer is directly contacting the second film layer and the intermediate film layer, and wherein the first auxiliary antiferroelectric induction layer and the second auxiliary antiferroelectric induction layer are hafnium-free layers.
16 . The semiconductor device according to claim 15 , wherein a thickness of the intermediate film layer is greater than thicknesses of the first film layer, the second film layer, the first auxiliary antiferroelectric induction layer and the second auxiliary antiferroelectric induction layer.
17 . A method of fabricating a semiconductor device comprising:
forming a first transistor over a substrate, wherein forming the first transistor comprises:
forming a semiconductive material layer disposed over the substrate;
forming a source region and a drain region, wherein the semiconductive material layer is disposed between the source region and the drain region;
forming a gate dielectric film stack disposed on the semiconductive material layer, wherein forming the gate dielectric film stack comprises:
forming a first film layer comprising hafnium and having a thickness of T 1 , wherein the first film layer is directly contacting the semiconductive material layer;
forming an intermediate film layer on the first film layer, wherein the intermediate film layer comprises hafnium and having a thickness of T 3 ; and
forming a second film layer on the intermediate film layer, wherein the second film layer comprises hafnium and having a thickness of T 2 , and the intermediate film layer is sandwiched in between the first film layer and the second film layer, and wherein a hafnium content of the intermediate film layer is lower than a hafnium content of the first film layer and a hafnium content of the second film layer, and wherein a ratio of the thickness T 3 to the thickness T 1 is in a range of 5:1 to 20:1, and a ratio of the thickness T 3 to the thickness T 2 is in a range of 5:1 to 20:1; and
forming a gate electrode on the gate dielectric film stack, and directly contacting the second film layer.
18 . The method according to claim 17 , wherein the first film layer and the second film layer are formed with a material of Hf X Zr (1-X) O 2 , and wherein X is in a range of 0.5 to 0.7.
19 . The method according to claim 17 , wherein the intermediate film layer is formed with a material of Hf Y Zr (1-Y) O 2 , and wherein Y is in a range of 0.3 to 0.5.
20 . The method according to claim 17 , wherein the intermediate film layer is formed with a first sub-layer in contact with the first film layer and a second sub-layer in contact with the second film layer, and wherein the method further comprises forming an antiferroelectric induction layer between the first sub-layer and the second sub-layer.