Semiconductor device and method for manufacturing the same

1 . A semiconductor device, comprising:

a buffer layer;

a barrier layer disposed on the buffer layer;

a nitride-based semiconductor layer disposed on the barrier layer and having a channel region and a doped region abutting against each other, wherein the nitride-based semiconductor layer further has an oxide region over the channel region, and wherein the nitride-based semiconductor layer has a bandgap less than a bandgap of the barrier layer, which forms a heterojunction therebetween, thereby generating a two-dimensional hole gas (2DHG) region adjacent to the heterojunction and thus forming a gallium nitride (GaN) buried-channel p-field-effect transistor (p-FET);

an isolation layer covering the nitride-based semiconductor layer, wherein the isolation layer covers the oxide region of the nitride-based semiconductor layer, and wherein the channel region is configured to act as a buried channel located between the oxide region of the nitride-based semiconductor layer and the barrier layer;

a gate electrode disposed over the isolation layer of the nitride-based semiconductor layer, wherein the gate electrode is disposed over the oxide region of the nitride-based semiconductor layer, and a portion of the isolation layer and the oxide region of the nitride-based semiconductor layer collectively form a staggered gate stack between the barrier layer and the gate electrode; and

a source electrode and a drain electrode disposed over the nitride-based semiconductor layer and at opposite sides of the gate electrode.

2 . The semiconductor device of claim 1 , wherein the nitride-based semiconductor layer has a trench to accommodate the portion of the isolation layer.

3 . The semiconductor device of claim 2 , wherein the oxide region of the nitride-based semiconductor layer is adjacent to a bottom of the trench, and wherein a thickness of the oxide region of the nitride-based semiconductor layer is less than a depth of the trench.

4 . The semiconductor device of claim 2 , wherein the portion of the isolation layer and the oxide region of the nitride-based semiconductor layer have the same width.

5 . The semiconductor device of claim 2 , wherein the isolation layer extends from a position over the top-most surface of the nitride-based semiconductor layer to the trench.

6 . The semiconductor device of claim 1 , wherein the nitride-based semiconductor layer comprises GaN and the doped region is formed by p-doped GaN.

7 . The semiconductor device of claim 1 , wherein the isolation layer wraps a bottom of the gate electrode.

8 . A method for manufacturing a semiconductor device, comprising:

forming a buffer layer on a substrate;

forming a barrier layer on the buffer layer;

forming a nitride-based semiconductor layer on the barrier layer, wherein the nitride-based semiconductor layer has a channel region and a doped region abutting against each other, and wherein the nitride-based semiconductor layer has a bandgap less than a bandgap of the barrier layer to form a heterojunction therebetween;

forming a recessed region in the nitride-based semiconductor layer and forming a buried channel corresponding to the channel region in the nitride-based semiconductor layer;

forming an oxide region over the buried channel in the nitride-based semiconductor layer such that the buried channel is located between the oxide region of the nitride-based semiconductor layer and the barrier layer;

forming an isolation layer covering the nitride-based semiconductor layer and the oxide region of the nitride-based semiconductor layer;

forming a gate electrode over the isolation layer and over the oxide region of the nitride-based semiconductor layer; and

forming a source electrode and a drain electrode that directly contact the nitride-based semiconductor layer at opposite sides of the gate electrode.

9 . The method of claim 8 , wherein the buried channel is formed by reducing a p-type doping concentration of a portion of the nitride-based semiconductor layer.

10 . The method of claim 9 , wherein the buried channel is formed by oxygen plasma treatment.

11 . The method of claim 8 , wherein the isolation layer is in contact with the oxide region of the nitride-based semiconductor layer so as to form a staggered gate stack comprising SiNx, GaON, or combinations thereof.

12 . The method of claim 8 , wherein the oxide region is formed by surface oxidation and subsequent high temperature annealing.

13 . The method of claim 12 , wherein the surface oxidation comprises exposing the nitride-based semiconductor layer to an oxygen-containing plasma or an oxygen-containing gas.

14 . The method of claim 12 , wherein the high-temperature annealing comprises annealing the nitride-based semiconductor layer at a temperature ranging from 500° C. to 1000° C.

15 . The method of claim 11 , wherein the oxide region of the nitride-based semiconductor layer is composed of gallium oxynitride (GaON), and a thickness of GaON measured from secondary-ion mass-spectroscopy has a full width at half maximum of 4.8 nm.

16 . The semiconductor device of claim 3 , wherein a distance from the topmost surface of the oxide region of the nitride-based semiconductor layer to the barrier layer is less than a distance from the topmost surface of the nitride-based semiconductor layer to the barrier layer.

17 . The semiconductor device of claim 16 , wherein the oxide region of the nitride-based semiconductor layer is composed of gallium oxynitride (GaON), and a thickness of GaON measured from secondary-ion mass-spectroscopy has a full width at half maximum of 4.8 nm.

18 . The semiconductor device of claim 1 , wherein the isolation layer and the oxide region of the nitride-based semiconductor layer comprise a dielectric material and semiconductor material, respectively, which have a type-II energy band alignment in the staggered gate stack, and the staggered gate stack comprises GaON, SiN x , or combinations thereof.