Semiconductor device and manufacturing method of semiconductor device

1 . A semiconductor device comprising:

a semiconductor layer having a first main surface and a second main surface and divided into an active region, an outer peripheral region, and an intermediate region, the outer peripheral region extending around a periphery of the active region, the intermediate region located between the active region and the outer peripheral region and extending around the periphery of the active region; and

a trench gate, wherein

the semiconductor layer includes:

a drift region of a first conductivity type located in the active region, the intermediate region and the outer peripheral region;

a body region of a second conductivity type located in the active region and the intermediate region and disposed above the drift region;

a source region of the first conductivity type located in the active region and the intermediate region and disposed above the body region;

a first contact region of the second conductivity type located in the active region, reaching the body region beyond the source region, and having a higher concentration of second conductivity-type impurities than the body region; and

a second contact region of the second conductivity type located in the intermediate region, reaching the body region beyond the source region, extending around the source region and the body region along peripheral edges of the source region and the body region, and having a higher concentration of the second conductivity-type impurities than the body region,

the trench gate is located in the active region and extends from the first main surface beyond the source region and the body region,

concentration distributions of the second conductivity-type impurities in a depth direction of the first contact region and the second contact region match with each other, and

the second contact region occupies a half or more range of the intermediate region in a direction connecting the active region and the outer peripheral region, and

the body region in the intermediate region is located only at a position closer to the active region than the second contact region.

2 . The semiconductor device according to claim 1 , wherein

depths of bottom surfaces of the first contact region and the second contact region are substantially equal to a depth of a bottom surface of the body region.

3 . The semiconductor device according to claim 1 , wherein

the semiconductor layer further includes a plurality of guard rings of the second conductivity type located in the outer peripheral region and extending around the periphery of the active region and a periphery of the intermediate region, and

the second contact region is in contact with an innermost guard ring in the plurality of guard rings.

4 . The semiconductor device according to claim 1 , wherein

the semiconductor layer further includes a current diffusion region of the first conductivity type located in the active region and the intermediate region, disposed between the drift region and the body region, and having a higher concentration of first conductivity-type impurities than the drift region, and

the current diffusion region is in contact with a side surface of the trench gate.

5 . The semiconductor device according to claim 1 , wherein

the first contact region includes a silicide layer disposed at a position in contact with a source electrode disposed on the first main surface of the semiconductor layer, and

the concentration distribution of the second conductivity-type impurities of the first contact region has a maximum concentration in a vicinity of a bottom surface of the silicide layer.

6 . The semiconductor device according to claim 1 , wherein

the semiconductor layer further includes a plurality of deep regions of the second conductivity type located in the active region and the intermediate region and disposed between the drift region and the body region,

the plurality of deep regions extends along a first direction when the semiconductor layer is seen in plan view, and is arranged at an interval therebetween in a second direction orthogonal to the first direction,

each of the plurality of deep regions extends from a bottom surface of the body region beyond a bottom surface of the trench gate, and

each of the plurality of deep regions is in contact with the second contact region in the intermediate region.

7 . The semiconductor device according to claim 6 , wherein

the first direction is parallel to a longitudinal direction of the trench gate when the semiconductor layer is seen in plan view, and

one side surface of the trench gate is covered by the first contact region and one of the plurality of deep regions.

8 . The semiconductor device according to claim 6 , wherein

the first direction intersects a longitudinal direction of the trench gate when the semiconductor layer is seen in plan view.

9 . The semiconductor device according to claim 1 , wherein

the semiconductor layer further includes a plurality of deep regions of the second conductivity type located in the active region and the intermediate region and disposed between the drift region and the body region,

the plurality of deep regions includes a plurality of upper deep regions and a plurality of lower deep regions disposed below the plurality of upper deep regions,

the plurality of upper deep regions extends along a first direction when the semiconductor layer is seen in plan view, and is arranged at an interval therebetween in a second direction orthogonal to the first direction,

each of the plurality of upper deep regions extends from a bottom surface of the body region beyond a bottom surface of the trench gate,

each of the plurality of upper deep regions is in contact with the second contact region in the intermediate region,

the plurality of lower deep regions extends in a third direction different from the first direction when the semiconductor layer is seen in plan view, and is arranged at an interval therebetween in a fourth direction orthogonal to the third direction, and

each of the plurality of lower deep regions is in contact with the plurality of upper deep regions.

10 . A semiconductor device comprising:

a semiconductor layer having a first main surface and a second main surface and divided into an active region, an outer peripheral region, and an intermediate region, the outer peripheral region extending around a periphery of the active region, the intermediate region located between the active region and the outer peripheral region and extending around the periphery of the active region; and

a trench gate, wherein

the semiconductor layer includes:

a drift region of a first conductivity type located in the active region, the intermediate region and the outer peripheral region;

a body region of a second conductivity type located in the active region and the intermediate region and disposed above the drift region;

a source region of the first conductivity type located in the active region and the intermediate region and disposed above the body region;

a first contact region of the second conductivity type located in the active region, reaching the body region beyond the source region, and having a higher concentration of second conductivity-type impurities than the body region; and

a second contact region of the second conductivity type located in the intermediate region, reaching the body region beyond the source region, extending around the source region along a peripheral edge of the source region, and having a higher concentration of the second conductivity-type impurities than the body region,

the trench gate is located in the active region and extends from the first main surface beyond the source region and the body region,

concentration distributions of the second conductivity-type impurities in a depth direction of the first contact region and the second contact region match with each other,

the second contact region occupies a half or more range of the intermediate region in a direction connecting the active region and the outer peripheral region,

the semiconductor layer further includes a plurality of guard rings of the second conductivity type located in the outer peripheral region and extending around the periphery of the active region and a periphery of the intermediate region, and

the second contact region is in contact with an innermost guard ring in the plurality of guard rings.

11 . A semiconductor device comprising:

a semiconductor layer having a first main surface and a second main surface and divided into an active region, an outer peripheral region, and an intermediate region, the outer peripheral region extending around a periphery of the active region, the intermediate region located between the active region and the outer peripheral region and extending around the periphery of the active region; and

a trench gate, wherein

the semiconductor layer includes:

a drift region of a first conductivity type located in the active region, the intermediate region and the outer peripheral region;

a body region of a second conductivity type located in the active region and the intermediate region and disposed above the drift region;

a source region of the first conductivity type located in the active region and the intermediate region and disposed above the body region;

a first contact region of the second conductivity type located in the active region,

reaching the body region beyond the source region, and having a higher concentration of second conductivity-type impurities than the body region; and

a second contact region of the second conductivity type located in the intermediate region, reaching the body region beyond the source region, extending around the source region along a peripheral edge of the source region, and having a higher concentration of the second conductivity-type impurities than the body region,

the trench gate is located in the active region and extends from the first main surface beyond the source region and the body region,

concentration distributions of the second conductivity-type impurities in a depth direction of the first contact region and the second contact region match with each other,

the second contact region occupies a half or more range of the intermediate region in a direction connecting the active region and the outer peripheral region,

the first contact region includes a silicide layer disposed at a position in contact with a source electrode disposed on the first main surface of the semiconductor layer, and

the concentration distribution of the second conductivity-type impurities of the first contact region has a maximum concentration in a vicinity of a bottom surface of the silicide layer.