Semiconductor device having isolation structure to reduce current leakage

1 . A method for forming a semiconductor device, comprising steps of:

forming a fin feature on a semiconductor substrate and forming a dummy gate feature over the fin feature, wherein the fin feature includes a sacrificial portion disposed over the semiconductor substrate, and a fin portion disposed over the sacrificial portion, and the dummy gate feature is disposed over and connected to the fin feature and the semiconductor substrate;

removing the sacrificial portion of the fin feature after the dummy gate feature is formed over the fin feature, thereby forming a gap between the semiconductor substrate and the fin portion of the fin feature;

forming a dielectric isolation layer that fills the gap between the semiconductor substrate and the fin portion of the fin feature for electrically isolating the fin portion of the fin feature from the semiconductor substrate;

forming, over the dielectric isolation layer, source/drain features that are connected to the fin portion of the fin feature; and

removing and replacing the dummy gate feature to form a gate electrode feature on the fin portion of the fin feature.

2 . The method according to claim 1 , further comprising, between the step of forming the dielectric isolation layer and the step of forming the source/drain features, a step of performing an annealing process.

3 . The method according to claim 1 , wherein the step of forming the source/drain features includes:

etching a part of the fin portion of the fin feature that is outside of a coverage of the dummy gate feature to form source/drain spaces; and

performing an epitaxy process to form the source/drain features in the source/drain spaces;

wherein the dielectric isolation layer is made of a first dielectric material, and the method further comprises, between the step of forming the dielectric isolation layer and the step of etching the part of the fin portion of the fin feature, a step of transforming a part of the dielectric isolation layer that is outside of a coverage of the fin feature from the first dielectric material into a second dielectric material that is different from the first dielectric material.

4 . The method according to claim 3 , wherein a plasma treatment is used to transform the part of the dielectric isolation layer from the first dielectric material into the second dielectric material.

5 . The method according to claim 4 , wherein each of the first dielectric material and the second dielectric material is a metal-based dielectric material.

6 . The method according to claim 5 , wherein the first dielectric material is one of a metal-based oxide and a metal-based nitride; and

wherein the plasma treatment uses a gas including nitrogen when the first dielectric material is the metal-based oxide, and uses a gas including oxygen when the first dielectric material is the metal-based nitride.

7 . The method according to claim 6 , wherein the gas used in the plasma treatment includes one of N 2 and NH 3 when the first dielectric material is the metal-based oxide, and includes one of O 2 and O 3 when the first dielectric material is the metal-based nitride.

8 . The method according to claim 5 , wherein the metal-based dielectric material includes one of Al, Hf and Zr.

9 . The method according to claim 4 , further comprising, between the plasma treatment and the step of forming the source/drain features, a step of performing an annealing process.

10 . The method according to claim 9 , wherein the annealing process has a process temperature ranging from 550° C. to 700° C.

11 . The method according to claim 3 , further comprising, between the step of forming the dielectric isolation layer and the step of transforming the part of the dielectric isolation layer from the first dielectric material into the second dielectric material, steps of:

coating a masking layer onto the dielectric isolation layer;

performing an etching back process to remove a portion of the masking layer that is disposed over the fin feature;

etching a portion of the dielectric isolation layer that is disposed over the fin feature; and

removing a remaining portion of the masking layer that covers the part of the dielectric isolation layer.

12 . The method according to claim 1 , wherein the sacrificial portion of the fin feature has a thickness in a range from 3 nm to 10 nm.

13 . The method according to claim 1 , wherein the fin portion of the fin feature is a multilayer stack that includes multiple semiconductor layers and multiple sacrificial layers that are alternately stacked together; and

wherein the sacrificial portion of the fin feature and the sacrificial layers of the fin portion of the fin feature are doped layers that have a same base material and a same dopant material, and a doping concentration of the sacrificial portion of the fin feature is different from that of the sacrificial layers of the fin portion of the fin feature.

14 . A method for forming a semiconductor circuit structure, comprising steps of:

forming a first sacrificial feature over a semiconductor substrate, and a first semiconductor feature over the first sacrificial feature, where the first sacrificial feature separates the first semiconductor feature from the semiconductor substrate;

removing the first sacrificial feature so as to disconnect the semiconductor substrate from a surface of the semiconductor feature that faces the semiconductor substrate by eliminating physical connections formed by the first sacrificial feature, thereby forming a gap between the semiconductor substrate and the semiconductor feature;

depositing a metal-based dielectric layer on the semiconductor substrate, wherein the metal-based dielectric layer is made of a first metal-based dielectric material, and a portion of the metal-based dielectric layer that fills the gap forms a first metal-based dielectric feature;

forming first source/drain features that are connected to the first semiconductor feature; and

forming a first gate feature on the first semiconductor feature,

wherein the method comprises a step of transforming another portion of the metal-based dielectric layer that is outside of a coverage of the semiconductor feature from the first metal-based dielectric material into a second metal-based dielectric material which is different from the first metal-based dielectric material.

15 . The method according to claim 14 , wherein the first metal-based dielectric feature separates the first source/drain features from the semiconductor substrate.

16 . The method according to claim 15 , further comprising steps of:

forming a second sacrificial feature over the semiconductor substrate, and a second semiconductor feature over the second sacrificial feature, where the second sacrificial feature separates the second semiconductor feature from the semiconductor substrate;

replacing the second sacrificial feature with a second metal-based dielectric feature that is same as the first metal-based dielectric feature in terms of material;

forming second source/drain features that are connected to the second semiconductor feature;

forming a second gate feature on the second semiconductor feature; and

forming a third metal-based dielectric feature that interconnects the first metal-based dielectric feature and the second metal-based dielectric feature, wherein the third metal-based dielectric feature is different from the first metal-based dielectric feature and the second metal-based dielectric feature in terms of material.

17 . The method according to claim 16 , wherein each of the first metal-based dielectric feature and the second metal-based dielectric feature includes an element of one of aluminum, hafnium and zirconium, and an element of one of nitrogen and oxygen; and

wherein the third metal-based dielectric feature includes an element of said one of aluminum, hafnium and zirconium, and an element of the other one of nitrogen and oxygen.

18 . A method for forming a semiconductor circuit structure, comprising steps of:

forming a sacrificial feature over a semiconductor substrate;

forming a first channel feature and a second channel feature over the sacrificial feature, wherein the first channel feature and the second channel feature are spaced apart from each other in a direction parallel to a surface of the semiconductor substrate;

replacing the sacrificial feature with a metal-based dielectric feature;

forming first source/drain features and second source/drain features over the metal-based dielectric feature, where the first source/drain features are connected to the first channel feature, and the second source/drain features are connected to the second channel feature;

transforming a portion of the metal-based dielectric feature from a first metal-based dielectric material into a second metal-based dielectric material that is different from the first metal-based dielectric material, wherein the portion of the metal-based dielectric feature is disposed between one of the first source/drain features and one of the second source/drain features when viewed from top; and

forming a first gate feature and a second gate feature on the first channel feature and the second channel feature, respectively.

19 . The method according to claim 18 , wherein the first metal-based dielectric material is one of a metal oxide and a metal nitride, and the second metal-based dielectric material is the other one of the metal oxide and the metal nitride.

20 . The method according to claim 14 , wherein the first metal-based dielectric material is one of a metal oxide and a metal nitride, and the second metal-based dielectric material is the other one of the metal oxide and the metal nitride.