Multi-gate transistor with concave and convex edges
A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.
1 . A semiconductor device, comprising:
a substrate; and
a transistor positioned on the substrate, wherein the transistor includes:
a shared gate region; and
a source and drain region having an active region,
wherein the active region of the source and drain region, as viewed from a top down view from above the shared gate region to the substrate, comprises a sidewall present along a sidewall of a channel region of the transistor and a concave outer wall extending outward from an edge of the sidewall of the active region of the source and drain region.
2 . The semiconductor device of claim 1 , further comprising a convex wall of the shared gate region, positioned adjacent to the concave outer wall of the active region.
3 . The semiconductor device of claim 2 , wherein an arrangement of the concave outer wall positioned adjacent to the convex wall of the shared gate region defines a sloped line gradually descending from an apex of the convex wall of the shared gate region to a nadir of the concave outer wall of the active region.
4 . The semiconductor device of claim 2 , wherein an arrangement of the concave outer wall positioned adjacent to the convex wall of the shared gate region defines a sinusoidal surface.
5 . The semiconductor device of claim 2 , wherein the convex wall is an inactive region of the shared gate region.
6 . The semiconductor device of claim 2 , wherein a first slope of the concave outer wall of the active region is aligned with a second slope of the convex wall of the shared gate region.
7 . The semiconductor device of claim 1 , wherein the source and drain region is metallic.
8 . The semiconductor device of claim 1 , wherein the semiconductor device is a multi-gate transistor.
9 . A semiconductor device, comprising:
a substrate; and
a transistor positioned on the substrate, wherein the transistor includes:
a shared gate region; and
a source and drain region having an active region,
wherein the active region of the source and drain region, as viewed from a top down view from above the shared gate region to the substrate, comprises a sidewall present along a sidewall of a channel region of the transistor and a curved outer wall extending outward from an edge of the sidewall of the active region of the source and drain region.
10 . The semiconductor device of claim 9 , wherein the curved outer wall is recessed inward from an extremity of the active region.
11 . The semiconductor device of claim 9 , wherein a nadir of the curved outer wall is proximate a center line of the active region.
12 . The semiconductor device of claim 9 , further comprising a sloped outer surface of the shared gate region, wherein an end of the curved outer wall of the active region is adjacent to the sloped outer surface of the shared gate region.
13 . The semiconductor device of claim 12 , wherein the sloped outer surface is an inactive region of the shared gate region.
14 . The semiconductor device of claim 9 , wherein the curved outer wall is symmetric about a center line of the active region.
15 . The semiconductor device of claim 9 , wherein the source and drain region is metallic.
16 . The semiconductor device of claim 9 , wherein the semiconductor device is a multi-gate transistor.