IP Library › Granted Patent US 12701746
Granted Patent B2
US 12701746 · App. 17/953,085 · Granted Aug 4, 2026

Integrated circuit structures having gate cut plug removed from trench contact

Inventors: Leonard P. Guler (Hillsboro, OR); Marie Conte (Hillsboro, OR); Charles H. Wallace (Portland, OR); Robert Joachim (Beaverton, OR); Shengsi Liu (Portland, OR); Saurabh Acharya (Hillsboro, OR); Nidhi Khandelwal (Portland, OR); Kyle T. Horak (Portland, OR); Robert Robinson (Beaverton, OR); Brandon Peters (Darien, IL)
Assignee: Intel Corporation
H10D30/6735H10D30/6213H10D30/6757H10D62/121
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Quick Facts
Patent No.
US 12701746
App. No.
17/953,085
Granted
Aug 4, 2026
Kind
B2
Abstract

Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.

Claims (48)

1 . An integrated circuit structure, comprising:

a vertical stack of horizontal nanowires;

a gate electrode over the vertical stack of horizontal nanowires;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a gate cut plug extending through the gate electrode and the dielectric sidewall spacer, the gate cut plug extending into but not entirely through the conductive trench contact, and the gate cut plug having an uppermost surface at a same level as an uppermost surface of the conductive trench contact.

2 . The integrated circuit structure of claim 1 , wherein the gate cut plug is conformal with an indentation in the conductive trench contact.

3 . The integrated circuit structure of claim 1 , wherein the gate cut plug has a portion beneath the conductive trench contact.

4 . The integrated circuit structure of claim 1 , further comprising a second conductive trench contact spaced apart from the conductive trench contact by a via bar structure, and a dielectric liner extending into but not entirely through a region between the second conductive trench contact and the via bar structure.

5 . The integrated circuit structure of claim 1 , further comprising an epitaxial source or drain structure at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact.

6 . An integrated circuit structure, comprising:

a fin;

a gate electrode over the fin;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a gate cut plug extending through the gate electrode and the dielectric sidewall spacer, the gate cut plug extending into but not entirely through the conductive trench contact, and the gate cut plug having an uppermost surface at a same level as an uppermost surface of the conductive trench contact.

7 . The integrated circuit structure of claim 6 , wherein the gate cut plug is conformal with an indentation in the conductive trench contact.

8 . The integrated circuit structure of claim 6 , wherein the gate cut plug has a portion beneath the conductive trench contact.

9 . The integrated circuit structure of claim 6 , further comprising a second conductive trench contact spaced apart from the conductive trench contact by a via bar structure, and a dielectric liner extending into but not entirely through a region between the second conductive trench contact and the via bar structure.

10 . The integrated circuit structure of claim 6 , further comprising an epitaxial source or drain structure at an end of the fin and beneath the conductive trench contact.

11 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a vertical stack of horizontal nanowires;

a gate electrode over the vertical stack of horizontal nanowires;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a gate cut plug extending through the gate electrode and the dielectric sidewall spacer, the gate cut plug extending into but not entirely through the conductive trench contact, and the gate cut plug having an uppermost surface at a same level as an uppermost surface of the conductive trench contact.

12 . The computing device of claim 11 , further comprising:

a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:

a communication chip coupled to the board.

14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a fin;

a gate electrode over the fin;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a gate cut plug extending through the gate electrode and the dielectric sidewall spacer, the gate cut plug extending into but not entirely through the conductive trench contact, and the gate cut plug having an uppermost surface at a same level as an uppermost surface of the conductive trench contact.

17 . The computing device of claim 16 , further comprising:

a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.