Semiconductor device with backside interconnection and method for forming the same

1 . A method, comprising:

forming a first fin and a second fin protruding from a frontside of a substrate;

forming a gate stack over the first and second fins;

forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin;

growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin, wherein the dielectric feature is disposed between the first and second epitaxial features;

performing an etching process on a backside of the substrate to form a backside trench, wherein the backside trench exposes the dielectric feature and the first and second epitaxial features;

forming a backside via in the backside trench, wherein the backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features; and

forming a frontside contact feature over the first and second epitaxial features, wherein the frontside contact feature and the backside via are electrically coupled to a same voltage line.

2 . The method of claim 1 , wherein the performing of the etching process includes etching the first and second fins from the backside of the substrate.

3 . The method of claim 2 , wherein the etching of the first and second fins forms a first via hole and a second via hole extending from the backside trench and exposing the first and second epitaxial features respectively, the first and second via holes are disposed on two opposing sides of the dielectric feature, and the forming of the backside via includes filling the first and second via holes and the backside trench with a conductive material.

4 . The method of claim 1 , further comprising:

forming an isolation structure surrounding the first and second fins, wherein the dielectric feature is disposed on the isolation structure,

wherein the performing of the etching process includes removing a portion of the isolation structure directly under the dielectric feature, thereby exposing the dielectric feature in the backside trench.

5 . The method of claim 4 , wherein after the performing of the etching process, the isolation structure remains on sidewalls of the dielectric feature.

6 . The method of claim 1 , further comprising:

prior to the forming the backside via, depositing a dielectric liner on sidewalls of the backside trench.

7 . The method of claim 1 , wherein each of the first and second epitaxial features includes a buffer epitaxial layer and a doped epitaxial layer over the buffer epitaxial layer, and the performing of the etching process includes removing the buffer epitaxial layer from the backside trench.

8 . The method of claim 1 , wherein the same voltage line is a grounding line.

9 . The method of claim 1 , wherein the forming of the frontside contact feature includes recessing a portion of the dielectric feature laterally between the first and second epitaxial features.

10 . A method of forming a memory circuit, comprising:

forming a first active region and a second active region over a substrate;

forming a gate structure over the substrate, wherein the gate structure has a first portion engaging the first active region in forming a first pull-down transistor of the memory circuit and a second portion engaging the second active region in forming a second pull-down transistor of the memory circuit;

forming a gate-cut feature isolating the first and second portions of the gate structure;

forming a first source/drain feature of the first pull-down transistor and a second source/drain feature of the second pull-down transistor, wherein the first and second source/drain features are disposed on two opposing sides of the gate-cut feature;

selectively etching the first and second active regions from a backside of the substrate to form a trench, wherein the trench exposes bottom surfaces of the first and second source/drain features and the gate-cut feature; and

depositing a conducive material in the trench to form a backside conductive feature landing on the bottom surfaces of the first and second source/drain features and the gate-cut feature.

11 . The method of claim 10 , wherein the backside conductive feature electrically couples the first and second source/drain features to a ground of the memory circuit.

12 . The method of claim 10 , wherein each of the first and second active regions includes a fin protruding from the substrate.

13 . The method of claim 10 , wherein each of the first and second active regions includes a plurality of channel layers vertically stacked above the substrate, and wherein each of the plurality of channel layers is wrapped around by the gate structure.

14 . The method of claim 10 , wherein the backside conductive feature includes first and second leg portions in contact with the first and second source/drain features respectively and a middle portion physically connecting the first and second leg portions, and wherein the middle portion is directly under the gate-cut feature.

15 . The method of claim 10 , wherein the backside conductive feature is a first backside conductive feature, the method further comprising:

forming a third active region over the substrate, wherein the second portion of the gate structure also engages the third active region in forming a pull-up transistor of the memory circuit;

forming a third source/drain feature of the pull-up transistor; and

forming a second backside conductive feature landing on a bottom surface of the third source/drain feature,

wherein the first and second backside conductive features are coupled to different voltage lines of the memory circuit, and wherein in a top view, an area of the first backside conductive feature is larger than that of the second backside conductive feature.

16 . The method of claim 15 , wherein the first backside conductive feature is coupled to a lower voltage than the second backside conductive feature.

17 . A method, comprising:

forming first and second active regions extending lengthwise along a first direction;

forming a gate stack extending lengthwise along a second direction different from the first direction;

forming a gate-cut feature dividing the gate stack into a first segment over the first active region and a second segment over the second active region, the gate-cut feature extending lengthwise along the first direction and disposed between the first and second active regions;

epitaxially growing a first epitaxial feature on the first active region;

epitaxially growing a second epitaxial feature on the second active region, the first and second epitaxial features disposed on two opposing sides of the gate-cut feature;

forming a backside conductive feature electrically coupled to the first and second epitaxial features, the backside conductive feature including a first leg portion landing on a bottom surface of the first epitaxial feature, a second leg portion landing on a bottom surface of the second epitaxial feature, and a middle portion positioned under the gate-cut feature and physically connecting the first and second leg portions; and

performing a planarization process to planarize a bottom surface of the backside conductive feature, wherein after the performing of the planarization process the middle portion of the backside conductive feature remains connecting the first and second leg portions.

18 . The method of claim 17 , wherein the middle portion interfaces with the gate-cut feature.

19 . The method of claim 17 , further comprising:

forming a frontside contact disposed on the first and second epitaxial features, wherein the gate-cut feature is vertically stacked between the frontside contact and the backside conductive feature.

20 . The method of claim 17 , further comprising:

forming a frontside contact feature over and electrically coupled to the first and second epitaxial features.