IP Library Granted Patent US 12701749
Granted Patent B2
US 12701749 · App. 18/240,313 · Granted Aug 4, 2026

Transistor, fabrication method thereof, and display apparatus comprising the same

Inventor: Jaehyun Kim (Paju-si, KR)
Assignee: LG Display Co., Ltd.
H10D30/6758H10D30/6728H10D30/6735H10D30/6755H10D30/6757H10D99/00H10W90/00
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Quick Facts
Patent No.
US 12701749
App. No.
18/240,313
Granted
Aug 4, 2026
Kind
B2
Abstract

A transistor, a fabricating method of the transistor, and a display apparatus comprising the transistor are provided. The transistor comprises a first electrode, nanorod on the first electrode, an active layer on the nanorod, a gate insulating layer on the active layer, a gate electrode on the active layer, and a second electrode connected to the active layer and disposed spaced apart from the first electrode, the first electrode has a pattern area, the nanorod is disposed on the pattern area, the nanorod has a diameter and height, the height of the nanorod is larger than the diameter of the nanorod, the active layer is disposed on a side surface of the nanorod, and connected to the first electrode.

Claims (57)

1 . A transistor comprising:

a first electrode;

a nanorod on the first electrode;

an active layer on the nanorod;

a gate insulating layer on the active layer;

a gate electrode on the gate insulating layer;

a second electrode connected to the active layer and disposed spaced apart from the first electrode; and

a first insulating layer disposed on a part of the first electrode, wherein:

the first electrode has a pattern area,

the nanorod is disposed on the pattern area,

the nanorod has a diameter and a height, the height of the nanorod is greater than the diameter of the nanorod,

the active layer is disposed on a side surface of the nanorod, and connected to the first electrode,

the active layer is disposed between the nanorod and the first insulating layer, and

the first electrode and the first insulating layer do not overlap each other in the pattern area.

2 . The transistor of claim 1 , wherein the first insulating layer overlaps at least a part of the first electrode.

3 . The transistor of claim 1 , wherein the nanorod is in contact with the first electrode in the pattern area, and

the nanorod is spaced apart from the first insulating layer.

4 . The transistor of claim 1 , wherein the active layer is in contact with a top surface and a side surface of the nanorod.

5 . The transistor of claim 1 , wherein the active layer is in contact with at least a part of the first electrode.

6 . The transistor of claim 1 , wherein the gate insulating layer is in contact with at least a part of the first insulating layer.

7 . The transistor of claim 1 , wherein the first electrode has a plurality of the pattern areas defined by the first insulating layer.

8 . The transistor of claim 1 , wherein the first insulating layer contains at least one of silicon oxide (SiOx) and aluminum oxide (Al 2 O 3 ).

9 . The transistor of claim 1 , wherein the nanorod includes at least one of ZnO, GaN, and a mixture including the same.

10 . The transistor of claim 1 , wherein the nanorod has a height in the range of 100 nm to 100 μm.

11 . The transistor of claim 1 , wherein the nanorod has a cylindrical or prismatic shape, and

the nanorod has a diameter in the range of 1 nm to 100 μm in a plan view.

12 . The transistor of claim 1 , wherein the nanorod has insulating property.

13 . The transistor of claim 1 , wherein the active layer includes an oxide semiconductor material.

14 . A display apparatus comprising:

a first transistor having at least one of sub-transistor;

a second transistor that is electrically connected to the first transistor and has a plurality of sub-transistors; and

a light emitting device connected to the second transistor;

wherein each of the sub-transistors comprises:

a first electrode;

a nanorod on the first electrode;

an active layer on the nanorod;

a gate insulating layer on the active layer;

a gate electrode on the gate insulating layer;

a second electrode connected to the active layer, and disposed spaced apart from the first electrode; and

a first insulating layer disposed on a part of the first electrode, wherein:

the first electrode has a pattern area,

the nanorod is disposed on the pattern area,

the active layer is disposed on a side surface of the nanorod, and connected to the first electrode,

the active layer is disposed between the nanorod and the first insulating layer, and

the first electrode and the first insulating layer do not overlap each other in the pattern area.

15 . The display apparatus of claim 14 , wherein the first transistor is a switching transistor, and

the second transistor is a driving transistor.

16 . The display apparatus of claim 14 , wherein the second transistor has a larger number of sub-transistors than the first transistor.

17 . The display apparatus of claim 14 , the light emitting device is an inorganic light emitting diode.

18 . The display apparatus of claim 14 , wherein the light emitting device comprises:

a n-type electrode;

a n-type semiconductor layer connected to the n-type electrode;

an active layer connected to the n-type semiconductor layer;

a p-type semiconductor layer connected to the active layer; and

a p-type electrode connected to the p-type semiconductor layer.

19 . The display apparatus of claim 14 , further comprising a second insulating layer disposed on the second electrode, and in contact with the light emitting device,

wherein the second insulating layer includes an adhesive polymer resin.