Doping profile for strained source/drain region

1 . An integrated chip, comprising:

a gate structure arranged over a substrate;

a source/drain region arranged within the substrate along a side of the gate structure, the source/drain region comprising:

a first layer lining interior sidewalls of the substrate and a horizontally extending surface of the substrate contacting the interior sidewalls of the substrate;

a second layer lining interior sidewalls of the first layer and a horizontally extending surface of the first layer contacting the interior sidewalls of the first layer on opposing sides of the first layer; and

wherein the first layer has a strain inducing component with a first strain inducing component concentration that continually decreases from outermost sidewalls of the first layer facing the substrate to the interior sidewalls of the first layer and the second layer has the strain inducing component with a second strain inducing component concentration that changes as distances from outermost sidewalls of the second layer increase.

2 . The integrated chip of claim 1 , wherein the first strain inducing component concentration continually decreases at a substantially constant rate between the outermost sidewalls of the first layer and the interior sidewalls of the first layer.

3 . The integrated chip of claim 1 , wherein the second strain inducing component concentration is larger than the first strain inducing component concentration and increases as the distances from the outermost sidewalls of the second layer increase.

4 . The integrated chip of claim 1 , wherein the source/drain region has a maximum strain inducing component concentration along an upper surface of the second layer.

5 . The integrated chip of claim 1 , wherein the first strain inducing component concentration continually decreases between a bottommost surface of the first layer and an upper surface of the first layer.

6 . The integrated chip of claim 5 , wherein the second strain inducing component concentration continually increases between a bottommost surface of the second layer and an upper surface of the second layer.

7 . The integrated chip of claim 1 , further comprising:

a second source/drain region arranged within the substrate along a second side of the gate structure opposing the side of the gate structure; and

a channel region disposed vertically below the gate structure and laterally between the source/drain region and the second source/drain region, wherein the first strain inducing component concentration decreases from a first value to a lower second value, the first value being directly between the second value and the channel region.

8 . The integrated chip of claim 1 , wherein the second strain inducing component concentration increases from an outermost sidewall of the second layer to within the second layer.

9 . The integrated chip of claim 1 , wherein the first strain inducing component concentration decreases along a first line extending through a first surface of the first layer and along a second line extending through a second surface of the first layer, the first line intersecting the second line above the first layer.

10 . The integrated chip of claim 1 , wherein the strain inducing component comprises material configured to induce compressive strain or tensile strain on a channel region underlying the gate structure.

11 . The integrated chip of claim 1 , wherein the horizontally extending surface of the first layer is set back from opposing ends of the horizontally extending surface of the substrate by non-zero distances.

12 . An integrated chip, comprising:

a substrate;

a gate structure disposed over an upper surface of the substrate;

source/drain regions arranged along opposing sides of the gate structure;

a channel region disposed vertically below the gate structure and laterally between the source/drain regions, wherein the source/drain regions respectively have a strain inducing component concentration profile that decreases from a first value to a lower second value at a first gradient and that decreases from the second value to a third value at a second gradient;

wherein the first gradient does not equal the second gradient; and

wherein the first value is a smaller vertical distance from the upper surface of the substrate than the second value, and the second value is a smaller vertical distance from the upper surface of the substrate than the third value.

13 . The integrated chip of claim 12 ,

wherein the source/drain regions respectively comprise a first region closest to the substrate and a second region that is separated from the substrate by the first region; and

wherein the first region has a first strain inducing component concentration profile that decreases in a first direction pointing away from the substrate and the second region has a second strain inducing component concentration profile that has a minimum value that is greater than a maximum value of the first strain inducing component concentration profile.

14 . The integrated chip of claim 13 , wherein the first strain inducing component concentration profile is discontinuous with the second strain inducing component concentration profile.

15 . The integrated chip of claim 12 , wherein the source/drain regions are disposed along a <111> surface of the substrate, the first value of the strain inducing component concentration profile being a first distance from the <111> surface and the second value being a second distance from the <111> surface, the first distance being smaller than the second distance.

16 . The integrated chip of claim 12 , wherein the strain inducing component concentration profile decreases along a first line extending through a first point along a first surface of the source/drain regions and along a second line extending through a second point along a second surface of the source/drain regions, the first line intersecting the second line above the first point and the second point.

17 . An integrated chip, comprising:

a gate structure arranged over a semiconductor substrate, wherein the semiconductor substrate comprises interior surfaces forming source/drain recesses along opposing sides of the gate structure;

source/drain regions arranged within the source/drain recesses; and

wherein the source/drain regions comprise a strain inducing component having a strain inducing component concentration profile that changes from a first concentration at a first position, to a second concentration at a second position overlying the first position, to a third concentration at a third position overlying the second position and vertically below a bottommost surface of the gate structure, the first concentration being larger than the second concentration and smaller than the third concentration.

18 . The integrated chip of claim 17 , wherein the strain inducing component concentration profile within the source/drain regions decreases along a first line extending through a first point along a first surface of the source/drain regions and along a second line extending through a second point along a second surface of the source/drain regions, the first line intersecting the second line above the first point and the second point.

19 . The integrated chip of claim 17 , wherein the strain inducing component concentration profile comprises a plurality of discontinuities along a line that is perpendicular to a bottom of the source/drain regions.

20 . The integrated chip of claim 17 , wherein the strain inducing component comprises germanium or silicon carbide.