Superjunction silicon carbide semiconductor device having trench gate structures formed on stacked layers of parallel pn junctions extending in different directions and method thereof

1 . A superjunction silicon carbide semiconductor device, comprising:

a silicon carbide semiconductor substrate of a first conductivity type, having a front surface and a back surface opposite to the front surface;

a first semiconductor layer of the first conductivity type, provided on the front surface of the substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the substrate;

a lower parallel pn structure provided at a surface of the first semiconductor layer, having a first surface and a second surface that are opposite to each other and parallel to the front surface of the substrate, and including a plurality of lower first columns of the first conductivity type and a plurality of lower second columns of a second conductivity type that are disposed repeatedly alternating with each other to form a stripe pattern on the second surface thereof, the lower first columns and the lower second columns extending in a first direction;

an upper parallel pn structure provided on the first surface of the lower parallel pn structure, having a first surface and a second surface that are opposite to each other and parallel to the front surface of the substrate, and including a plurality of upper first columns of the first conductivity type and a plurality of upper second columns of the second conductivity type that are disposed repeatedly alternating with each other to form a stripe pattern on the second surface thereof, the upper first columns and the upper second columns extending in a second direction different than the first direction;

a second semiconductor layer of the second conductivity type, provided on a surface of the upper parallel pn structure;

a first semiconductor region of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer;

a plurality of trenches, each of which penetrates the first semiconductor region and the second semiconductor layer, and reaches the upper parallel pn structure;

a plurality of gate electrodes, each of which is provided in a corresponding one of the trenches via a gate insulating film;

an interlayer insulating film provided on the gate electrodes;

a first electrode in contact with the second semiconductor layer and the first semiconductor region; and

a second electrode provided at the back surface of the substrate, wherein

at the second surface of the upper parallel pn structure, in a direction orthogonal to the second direction, an arithmetic product of a width and an impurity concentration of each of the plurality of upper first columns and an arithmetic product of a width and an impurity concentration of each of the plurality of upper second columns differ by no more than 5% of each other, whereby the upper parallel pn structure is charge balanced as the superjunction silicon carbide semiconductor device,

an impurity concentration of the upper first columns is lower than an impurity concentration of the first semiconductor region and higher than the impurity concentration of the first semiconductor layer,

a bottom of each of the plurality of trenches is embedded in a corresponding one of the plurality of upper second columns, and

the impurity concentration of each of the plurality of upper second columns and an impurity concentration of each of the plurality of lower second columns are higher than an impurity concentration of the second semiconductor layer.

2 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein

the trenches form a planar stripe pattern, and

a lower end of each of the upper second columns is provided closer to the second electrode than is a bottom of each of the trenches, and each of the upper second columns extends in a direction parallel to directions in which the trenches extend.

3 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein

the trenches form a planar stripe pattern, and

a lower end of each of the upper second columns is provided closer to the second electrode than is a bottom of each of the trenches, and each of the upper second columns extends in a direction different than directions in which the trenches extend.

4 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein

the upper parallel pn structure or the lower parallel pn structure is configured by a multi-level parallel pn structure in which a plurality of first columns of the first conductivity type are disposed repeatedly alternating with a plurality of second columns of the second conductivity type in each level of the multi-level parallel pn structure, to form a stripe pattern in respective planes of levels of the multi-level parallel pn structure that are parallel to the front surface, and

the first columns and the second columns in one of the planes extend in the first direction, and the first columns and the second columns in another of the planes beneath the one plane extend in the second direction.

5 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein the first direction and the second direction are 90° apart.

6 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein the first direction and the second direction are 60° apart.

7 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein

at the second surface of the lower parallel pn structure in a direction orthogonal to the first direction, an arithmetic product of a width and an impurity concentration of each of the plurality of lower first columns and an arithmetic product of a width and the impurity concentration of each of the plurality of lower second columns differ by no more than 5% of each other, whereby the lower parallel pn structure is charge balanced as the superjunction silicon carbide semiconductor device.

8 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein ones of the plurality of lower first columns or the plurality of lower second columns in the lower parallel pn structure are epitaxial layers doped with impurities of one of the first conductivity type or the second conductivity type, and the other ones of the plurality of lower first columns or the plurality of lower second columns in the lower parallel pn structure are ion implanted regions containing impurities of the other one of the first conductivity type or the second conductivity type.

9 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein each of an adjacent two of the trenches that are adjacent to each other reaches a respective one of two of the upper second columns in the upper parallel pn structure, another one of the upper second columns formed between the two of the upper second columns being disposed between the adjacent two of the trenches.

10 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein a bottom of each of the lower second columns is located at a position deeper than a bottom of a region of the second conductivity type of an edge termination region surrounding a periphery of an active region where the first electrode is provided.

11 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein a bottom of each of the lower first columns and a bottom of each of the lower second columns are in contact with the first semiconductor layer.

12 . The superjunction silicon carbide semiconductor device according to claim 1 , wherein the lower first columns and the lower second columns of the lower parallel pn structure each have the same thickness.

13 . A method of manufacturing a superjunction silicon carbide semiconductor device, the method comprising:

forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the substrate;

forming, at a surface of the first semiconductor layer, a lower parallel pn structure having a first surface and a second surface that are opposite to each other and parallel to the front surface of the substrate, and including a plurality of lower first columns of the first conductivity type and a plurality of lower second columns of a second conductivity type that are disposed repeatedly alternating with each other to form a stripe pattern on the second surface thereof, the lower first columns and the lower second columns extending in a first direction;

forming, on the first surface of the lower parallel pn structure, an upper parallel pn structure having a first surface and a second surface that are opposite to each other and parallel to the front surface of the substrate, and including a plurality of upper first columns of the first conductivity type and a plurality of upper second columns of the second conductivity type that are disposed repeatedly alternating with each other to form a stripe pattern on the second surface thereof, the upper first columns and the upper second columns extending in a second direction different than the first direction;

forming a second semiconductor layer of the second conductivity type on a surface of the upper parallel pn structure;

selectively forming first semiconductor regions of the first conductivity type in a surface layer of the second semiconductor layer;

forming a plurality of trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the upper parallel pn structure;

forming a plurality of gate electrodes in the trenches, each of the gate electrodes being provided in a corresponding one of the trenches, via a gate insulating film;

forming an interlayer insulating film on the gate electrodes;

forming a first electrode in contact with the second semiconductor layer and the first semiconductor regions; and

forming a second electrode on a back surface of the substrate, wherein

at the second surface of the upper parallel pn structure, in a direction orthogonal to the second direction, an arithmetic product of a width and an impurity concentration of each of the plurality of upper first columns and an arithmetic product of a width and an impurity concentration of each of the plurality of upper second columns differ by no more than 5% of each other, whereby the upper parallel pn structure is charge balanced as the superjunction silicon carbide semiconductor device,

an impurity concentration of the upper first columns is lower than an impurity concentration of the first semiconductor regions and higher than the impurity concentration of the first semiconductor layer,

a bottom of each of the plurality of trenches is embedded in a corresponding one of the plurality of upper second columns, and

the impurity concentration of each of the plurality of upper second columns and an impurity concentration of each of the plurality of lower second columns are higher than an impurity concentration of the second semiconductor layer.

14 . The method of manufacturing a superjunction silicon carbide semiconductor device according to claim 13 , wherein

at the second surface of the lower parallel pn structure in a direction orthogonal to the first direction, an arithmetic product of a width and an impurity concentration of each of the plurality of lower first columns and an arithmetic product of a width and the impurity concentration of each of the plurality of lower second columns differ by no more than 5% of each other, whereby the lower parallel pn structure is charge balanced as the superjunction silicon carbide semiconductor device.

15 . The method of manufacturing a superjunction silicon carbide semiconductor device according to claim 7 , wherein the forming a lower parallel pn structure includes

forming an epitaxial layer doped with impurities of one of the first conductivity type or the second conductivity type, and

implanting impurities of the other one of the first conductivity type or the second conductivity type in the epitaxial layer, using a mask, whereby ones of the plurality of lower first columns or the plurality of lower second columns in the lower parallel pn structure are formed by the epitaxial layer doped with the impurities of one of the first conductivity type or the second conductivity type, and the other ones of the plurality of lower first columns or the plurality of lower second columns in the lower parallel pn structure are formed by ion implanted regions containing the impurities of the other one of the first conductivity type or the second conductivity type.

16 . The method of manufacturing a superjunction silicon carbide semiconductor device according to claim 13 , wherein the forming a plurality of trenches includes forming each of an adjacent two of the trenches that are adjacent to each other so as to reach a respective one of two of the upper second columns in the upper parallel pn structure and so that another one of the upper second columns formed between the two of the upper second columns is disposed between the adjacent two of the trenches.

17 . The method of manufacturing a superjunction silicon carbide semiconductor device according to claim 13 , wherein a bottom of each of the lower second columns is located at a position deeper than a bottom of a region of the second conductivity type of an edge termination region surrounding a periphery of an active region where the first electrode is provided.

18 . The method of manufacturing a superjunction silicon carbide semiconductor device according to claim 13 , wherein a bottom of each of the lower first columns and a bottom of each of the lower second columns are in contact with the first semiconductor layer.