Semiconductor device having nanosheet transistor and methods of fabrication thereof

1 . A semiconductor device structure, comprising:

a plurality of semiconductor layers vertically stacked over a substrate;

a source/drain feature in contact with each of the plurality of the semiconductor layers;

an inner spacer disposed between two adjacent semiconductor layers;

a gate electrode layer surrounding a portion of at least one of the plurality of the semiconductor layers;

a gate dielectric layer disposed between at least one of the plurality of semiconductor layers and the gate electrode layer;

a gate spacer in contact with a portion of the gate dielectric layer;

a first cap layer comprising:

a first portion disposed between and in contact with the source/drain feature and the gate spacer; and

a second portion disposed between and in contact with gate spacer and the inner spacer;

a contact etch stop layer (CESL) disposed over the source/drain feature; and

a second cap layer disposed between and in contact with the gate spacer and the CESL.

2 . The semiconductor device structure of claim 1 , wherein the second portion is extended so that the second portion is disposed between and in contact with the gate dielectric layer and the inner spacer.

3 . The semiconductor device structure of claim 1 , wherein a portion of the gate dielectric layer is disposed between and in contact with the gate spacer and the gate electrode layer.

4 . The semiconductor device structure of claim 1 , wherein the first cap layer further comprises:

a third portion disposed between and in contact with the inner spacer and the gate dielectric layer.

5 . The semiconductor device structure of claim 4 , wherein the third portion of the first cap layer has a curved profile.

6 . The semiconductor device structure of claim 1 , wherein the first and second cap layers are formed of a nitride-based material.

7 . The semiconductor device structure of claim 5 , wherein the third portion of the first cap layer has a concave profile.

8 . A semiconductor device structure, comprising:

a plurality of semiconductor layers vertically stacked over a substrate;

a source/drain feature in contact with the plurality of the semiconductor layers;

an inner spacer disposed between two adjacent semiconductor layers;

a gate electrode layer surrounding a portion of at least one of the plurality of the semiconductor layers;

a gate dielectric layer disposed between the semiconductor layer and the gate electrode layer;

a gate spacer in contact with a portion of the gate dielectric layer; and

a cap layer, comprising:

a first portion disposed between and in contact with the source/drain feature and the gate spacer, the first portion having a first thickness;

a second portion disposed between and in contact with gate spacer and the inner spacer, the second portion having a second thickness; and

a third portion disposed between and in contact with the inner spacer and the gate dielectric layer, the third portion having a third thickness,

wherein the third thickness is less than the first thickness.

9 . The semiconductor device structure of claim 8 , wherein the second thickness is greater than the third thickness.

10 . The semiconductor device structure of claim 8 , wherein the cap layer is formed of a nitride-based material.

11 . The semiconductor device structure of claim 10 , wherein the cap layer is SiGeN.

12 . The semiconductor device structure of claim 10 , wherein the cap layer has a thickness of about 3 Å to about 30 Å.

13 . A semiconductor device structure, comprising:

a plurality of semiconductor layers vertically stacked over a substrate;

a source/drain feature in contact with each of the plurality of the semiconductor layers;

a first gate dielectric layer surrounding a portion of each of the plurality of the semiconductor layers;

a first cap layer disposed between the source/drain feature and the first gate dielectric layer, wherein the first cap layer has a first side in contact with the source/drain feature;

a gate spacer disposed between and in contact with the first gate dielectric layer and a second side of the first cap layer;

an inner spacer disposed between and in contact with the first gate dielectric layer and the second side of the first cap layer;

a contact etch stop layer (CESL) disposed over the source/drain feature; and

a second cap layer disposed between and in contact with the gate spacer and the CESL.

14 . The semiconductor device structure of claim 13 , further comprising:

a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers; and

a second gate dielectric layer disposed between the source/drain feature and the gate electrode layer.

15 . The semiconductor device structure of claim 14 , wherein the second gate dielectric layer is in contact with the first gate dielectric layer and the second side of the first cap layer, wherein the second gate dielectric layer is made of a material chemically different than the first gate dielectric layer.

16 . The semiconductor device structure of claim 13 , wherein the first cap layer surrounds a portion of at least one of the semiconductor layers.

17 . The semiconductor device structure of claim 13 , wherein the first and second cap layers are formed of a nitride-based material.

18 . The semiconductor device structure of claim 17 , wherein the second cap layer is disposed between and in contact with the CESL and the gate spacer.

19 . The semiconductor device structure of claim 17 , wherein the second cap layer further comprises:

a first sublayer in contact with the first gate dielectric layer, wherein the first sublayer has a first nitrogen content; and

a second sublayer disposed between and in contact with the gate spacer and the first sublayer, the second sublayer has a second nitrogen content less than the first nitrogen content.

20 . The semiconductor device structure of claim 13 , wherein the cap layer is SiGeN.