Manufacturing method of integrated circuit structure
An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.
1 . A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises a first channel layer, a first sacrificial layer, a second sacrificial layer, and a second channel layer sequentially stacked from bottom to top;
forming a dummy gate structure to cover the fin structure;
forming a gate spacer to surround the dummy gate structure;
forming first source/drain epitaxial structures on opposite sides of the first channel layer and second source/drain epitaxial structures on opposite sides of the second channel layer;
removing the dummy gate structure to form a gate trench defined by the gate spacer;
removing the first sacrificial layer to release the first channel layer;
forming a first fork-sheet gate structure in the gate trench to surround the first channel layer, wherein the first fork-sheet gate structure is in contact with the second sacrificial layer;
removing the second sacrificial layer to release the second channel layer; and
forming a second fork-sheet gate structure in the gate trench to surround the second channel layer.
2 . The method of claim 1 , further comprising forming a dielectric blocking layer on an end surface of the second channel layer prior to forming the first fork-sheet gate structure.
3 . The method of claim 2 , further comprising forming an inner spacer on an end surface of the first sacrificial layer prior to forming the dielectric blocking layer.
4 . The method of claim 1 , wherein the first channel layer, the first sacrificial layer, the second sacrificial layer, and the second channel layer have different germanium concentrations.
5 . The method of claim 1 , wherein the first fork-sheet gate structure is exposed after removing the second sacrificial layer.
6 . The method of claim 1 , wherein forming the second fork-sheet gate structure comprises:
depositing a gate dielectric layer in the gate trench and in contact with the first fork-sheet gate structure and the second channel layer; and
depositing a metal layer over the gate dielectric layer.
7 . The method of claim 6 , wherein a bottom surface of the metal layer of the second fork-sheet gate structure is lower than a bottom surface of the first channel layer.
8 . A method comprising:
forming a stacking structure over a substrate, wherein the stacking structure comprises a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially stacked from bottom to top;
forming a dummy gate structure across the stacking structure;
forming a gate spacer structure surrounding the dummy gate structure;
removing the dummy gate structure to form a gate trench defined by the gate spacer structure;
after forming the gate trench, recessing the second channel layer to form a first recess in the second channel layer;
forming a first dielectric structure in the first recess of the second channel layer;
after forming the first dielectric structure, removing the first sacrificial layer to release the first channel layer;
forming a first metal gate structure in the gate trench and surrounding the first channel layer;
removing the second sacrificial layer to release the second channel layer; and
forming a second metal gate structure in the gate trench and surrounding the second channel layer.
9 . The method of claim 8 , wherein after forming the second metal gate structure, the first dielectric structure is in contact with the first metal gate structure and the second metal gate structure.
10 . The method of claim 8 , further comprising:
recessing the first channel layer to form a second recess in the first channel layer after forming the first metal gate structure and prior to removing the second sacrificial layer; and
forming a second dielectric structure in the second recess prior to removing the second sacrificial layer.
11 . The method of claim 10 , wherein the second recess is defined by the first metal gate structure and the first channel layer.
12 . The method of claim 10 , wherein after forming the second metal gate structure, the second dielectric structure is in contact with the first metal gate structure and the second metal gate structure.
13 . The method of claim 8 , further comprising:
depositing an interlayer dielectric (ILD) layer over the first metal gate structure and the second metal gate structure;
forming a first gate via in the ILD layer and connected to the first metal gate structure; and
forming a second gate via in the ILD layer and connected to the second metal gate structure.
14 . The method of claim 13 , wherein a bottom of the first gate via is at a position substantially level with a bottom of the second gate via.
15 . A method comprising:
forming a stacking structure over a protruding portion of a substrate, wherein the stacking structure comprises a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially stacked from bottom to top;
forming a first isolation structure and a second isolation structure on opposite sides of the protruding portion of the substrate;
forming a dummy gate structure across the stacking structure;
forming a gate spacer structure to surround the dummy gate structure;
removing the dummy gate structure to form a gate trench defined by the gate spacer structure;
removing the first sacrificial layer to release the first channel layer;
forming a first metal gate structure in the gate trench and in contact with the first channel layer and the first isolation structure;
forming a first dielectric structure on a sidewall of the first channel layer after forming the first metal gate structure;
after forming the first dielectric structure, removing the second sacrificial layer to release the second channel layer; and
forming a second metal gate structure in the gate trench and in contact with the second channel layer and the second isolation structure.
16 . The method of claim 15 , wherein after forming the second metal gate structure, a top surface of the first metal gate structure is higher than a top surface of the second channel layer.
17 . The method of claim 15 , wherein after forming the first metal gate structure, the second isolation structure is exposed in the gate trench.
18 . The method of claim 15 , wherein the first dielectric structure is in contact with the first metal gate structure.
19 . The method of claim 15 , wherein a height of the first metal gate structure is substantially the same as a height of the second metal gate structure.
20 . The method of claim 15 , further comprising forming a second dielectric structure on a sidewall of the second channel layer prior to forming the first metal gate structure.