Semiconductor devices including a lower power interconnection line and methods of manufacturing the same

1 . A semiconductor device, comprising:

a substrate having a first and second active patterns therein;

a first and second source/drain patterns extending on the first and second active patterns, respectively;

an active contact on the first and second source/drain patterns;

an upper contact extending from the active contact towards the substrate, and between the first and second active patterns;

a lower power interconnection line buried in a lower portion of the substrate, said lower power interconnection line comprising:

a buried interconnection portion having a line shape and extending in a first direction; and

a lower contact portion extending in a second direction vertically from the buried interconnection portion to a bottom surface of the upper contact, the second direction different from the first direction; and

a barrier pattern extending between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.

2 . The device of claim 1 , wherein a width of the upper contact becomes progressively smaller in a direction extending toward a bottom surface of the substrate; and wherein a width of the lower contact portion becomes progressively greater toward the bottom surface of the substrate.

3 . The device of claim 2 , wherein the upper contact and the lower contact portion have a generally sandglass shape when viewed in transverse cross-section.

4 . The device of claim 1 , wherein the lower power interconnection line further comprises a connection portion extending between the buried interconnection portion and the lower contact portion; wherein the buried interconnection portion has a first width; wherein the connection portion has a second width less than the first width; wherein the lower contact portion has a third width less than the second width; and wherein a ratio of the second width to the third width is greater than a ratio of the first width to the second width.

5 . The device of claim 1 , wherein the lower contact portion is self-aligned with the upper contact.

6 . The device of claim 1 , wherein the buried interconnection portion is offset from the lower contact portion.

7 . The device of claim 1 , further comprising a power delivery network layer extending on a bottom surface of the substrate; and wherein the power delivery network layer is configured to apply a source voltage or a drain voltage to the lower power interconnection line.

8 . The device of claim 1 , further comprising:

a channel pattern extending on each of the first and second active patterns; and

a gate electrode on the channel pattern; and

wherein the channel pattern comprises a plurality of semiconductor patterns, which are stacked and spaced apart from each other.

9 . The device of claim 1 , wherein the lower power interconnection line extends along a boundary between adjacent logic cells.

10 . The device of claim 1 , wherein a conductive pattern of the upper contact and a conductive pattern of the lower power interconnection line include different metals.

11 . A semiconductor device, comprising:

a substrate having first and second active patterns therein;

first and second source/drain patterns extending on the first and second active patterns, respectively;

an active contact on the first and second source/drain patterns;

an upper contact extending from the active contact towards the substrate, and between the first and second active patterns; and

a lower power interconnection line buried in a lower portion of the substrate, said lower power interconnection line comprising:

a buried interconnection portion having a line shape and extending in a first direction;

a lower contact portion extending vertically in a second direction from the buried interconnection portion to a bottom surface of the upper contact, the second direction different from the first direction; and

a connection portion extending between the buried interconnection portion and the lower contact portion; and

wherein the buried interconnection portion has a first width, the connection portion has a second width less than the first width, the lower contact portion has a third width less than the second width, and a ratio of the second width to the third width is greater than a ratio of the first width to the second width.

12 . The device of claim 11 , wherein the buried interconnection portion, the lower contact portion and the connection portion are connected to each other in a single body.

13 . The device of claim 11 , further comprising a power delivery network layer provided on a bottom surface of the substrate; and wherein the power delivery network layer is configured to apply a source voltage or a drain voltage to the lower power interconnection line.

14 . The device of claim 11 , wherein a width of the upper contact becomes progressively smaller in a direction towards a bottom surface of the substrate; and wherein the third width of the lower contact portion becomes progressively larger in a direction towards the bottom surface of the substrate.

15 . The device of claim 14 , wherein the upper contact and the lower contact portion have a generally sandglass shape when viewed in transverse cross-section.

16 . A semiconductor device, comprising:

a substrate having first and second active regions therein, which are spaced apart from each other in a first direction;

first and second active patterns on the first and second active regions, respectively;

a first channel pattern and a first source/drain pattern on the first active pattern;

a second channel pattern and a second source/drain pattern on the second active pattern, said second source/drain pattern having the same conductivity type as the first source/drain pattern;

a gate electrode on the first and second channel patterns;

a gate insulating layer extending between the gate electrode and the first and second channel patterns;

a gate spacer on a sidewall of the gate electrode;

a gate capping pattern on a top surface of the gate electrode;

a gate cutting pattern, which penetrates the gate electrode between the first and second channel patterns;

an interlayer insulating layer covering the first and second source/drain patterns and the gate capping pattern;

an active contact penetrating the interlayer insulating layer so as to be electrically connected to the first and second source/drain patterns;

metal-semiconductor compound layers extending between the active contact and corresponding ones of the first and second source/drain patterns;

a gate contact penetrating the interlayer insulating layer and the gate capping pattern so as to be electrically connected to the gate electrode;

a first metal layer on the interlayer insulating layer, the first metal layer including a first interconnection line electrically connected to the gate contact;

a second metal layer on the first metal layer, the second metal layer including a second interconnection line electrically connected to the first metal layer;

an upper contact extending from the active contact toward the substrate, and between the first and second active patterns;

a lower power interconnection line, which is buried in a lower portion of the substrate, vertically overlaps with the gate cutting pattern, and extends in a second direction orthogonal to the first direction, said lower power interconnection line comprising:

a buried interconnection portion having a line shape extending in the second direction; and

a lower contact portion vertically extending in a third direction from the buried interconnection portion to a bottom surface of the upper contact; and

a power delivery network layer extending on a bottom surface of the substrate.

17 . The device of claim 16 , wherein the lower power interconnection line extends along a boundary between the first active region and the second active region.

18 . The device of claim 16 , wherein a width of the upper contact becomes progressively smaller in a direction towards the bottom surface of the substrate; and wherein a width of the lower contact portion becomes progressively larger in a direction towards the bottom surface of the substrate.

19 . The device of claim 18 , wherein the upper contact and the lower contact portion have a generally sandglass shape when viewed in transverse cross-section.

20 . The device of claim 16 , wherein the lower power interconnection line further comprises a connection portion extending between the buried interconnection portion and the lower contact portion; and wherein the buried interconnection portion has a first width, the connection portion has a second width less than the first width, the lower contact portion has a third width less than the second width, and a ratio of the second width to the third width is greater than a ratio of the first width to the second width.