IP Library Granted Patent US 12701760
Granted Patent B2
US 12701760 · App. 18/485,850 · Granted Aug 4, 2026

Semiconductor device and manufacturing method thereof

Inventors: Yu-Chang Lin (Hsinchu City, TW); Sih-Jie Liu (Hsinchu County, TW); Po-Kang Ho (Taoyuan City, TW); Liang-Yin Chen (Hsinchu City, TW); Tsai-Yu Huang (Taoyuan City, TW); Chi On Chui (Hsinchu City, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D62/151H10D30/014H10D30/43H10D30/6729H10D30/6735H10D62/121H10D64/017H10D84/0167H10D84/017H10D84/0186H10D84/038H10D84/85H10P30/204H10P30/21H10P32/1406H10P32/171
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Quick Facts
Patent No.
US 12701760
App. No.
18/485,850
Granted
Aug 4, 2026
Kind
B2
Abstract

A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.

Claims (44)

1 . A method for manufacturing a semiconductor device, comprising:

forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other;

forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species;

implanting fluorine ions into the source/drain epitaxial structure;

after implanting the fluorine ions into the source/drain epitaxial structure, performing a first annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and

forming a source/drain contact over the source/drain epitaxial structure.

2 . The method of claim 1 , wherein the p-type doping species is boron.

3 . The method of claim 1 , wherein the fluorine ions are implanted into the source/drain epitaxial structure by a projected range, and a position below a top surface of the source/drain epitaxial structure by the projected range is higher than a bottom surface of the topmost one of the semiconductor layers and lower than a top surface of the topmost one of the semiconductor layers.

4 . The method of claim 1 , wherein the annealing process is performed such that a concentration of the p-type doping species in the side region of the topmost one of the semiconductor layers is greater than about 1E19 atoms/cm 3 .

5 . The method of claim 1 , further comprising:

forming a gate structure over the semiconductor layers; and

forming a gate spacer alongside the gate structure, wherein the side region of the topmost one of the semiconductor layers is at least directly below the gate spacer.

6 . The method of claim 5 , wherein the side region of the topmost one of the semiconductor layers is further directly below the gate structure.

7 . The method of claim 1 , wherein implanting the fluorine ions into the source/drain epitaxial structure is performed such that a region of the source/drain epitaxial structure comprises the fluorine ions.

8 . The method of claim 7 , wherein forming the source/drain contact is performed such that the region of the source/drain epitaxial structure comprising the fluorine ions is partially removed.

9 . The method of claim 7 , wherein forming the source/drain contact is performed such that the region of the source/drain epitaxial structure comprising the fluorine ions is entirely removed.

10 . A method for manufacturing a semiconductor device, comprising:

forming a plurality of first semiconductor layers vertically stacked over a substrate, wherein the first semiconductor layers are vertically spaced apart from each other;

forming a plurality of second semiconductor layers vertically stacked over a substrate, wherein the second semiconductor layers are vertically spaced apart from each other;

forming a p-type source/drain epitaxial structure on sides of the first semiconductor layers;

performing an ion implantation process and a first annealing process to diffuse a p-type doping species in the p-type source/drain epitaxial structure into a topmost one of the first semiconductor layers;

after the ion implantation process and the annealing process, forming a n-type source/drain epitaxial structure on sides of the second semiconductor layers;

performing a second annealing process to activate the p-type source/drain epitaxial structure and the n-type source/drain epitaxial structure;

forming a first source/drain contact over the p-type source/drain epitaxial structure; and

forming a second source/drain contact over the n-type source/drain epitaxial structure.

11 . The method of claim 10 , wherein the second annealing process is performed at a temperature higher than a temperature of the first annealing process.

12 . The method of claim 10 , wherein the ion implantation process is performed such that the p-type source/drain epitaxial structure has a defect-rich region that has a higher defect concentration than a defect concentration of a portion of the p-type source/drain epitaxial structure below the defect-rich region.

13 . The method of claim 12 , wherein forming the first source/drain contact is performed such that the first source/drain contact is landed on the defect-rich region of the p-type source/drain epitaxial structure.

14 . The method of claim 10 , further comprising:

forming a gate structure over the first semiconductor layers and the second semiconductor layers;

forming a gate spacer alongside the gate structure;

before the ion implantation process and the first annealing process, depositing a metal-containing compound layer over a sidewall of the gate spacer and a top surface of the p-type source/drain epitaxial structure; and

etching the metal-containing compound layer to expose the top surface of the p-type source/drain epitaxial structure.

15 . The method of claim 14 , further comprising:

after the first annealing process, removing the metal-containing compound layer from the sidewall of the gate spacer.

16 . A semiconductor device, comprising:

a plurality of semiconductor layers vertically spaced apart from each other;

a gate structure wrapping around the semiconductor layers;

a gate spacer alongside the gate structure; and

a p-type source/drain epitaxial structure on sides of the semiconductor layers, wherein the p-type source/drain epitaxial structure comprises a p-type dopant species, and a side portion of a topmost one of the semiconductor layers directly below the gate spacer has a concentration of the p-type dopant species greater than that of a side portion of a second topmost one of the semiconductor layers.

17 . The semiconductor device of claim 16 , wherein the p-type dopant species is boron.

18 . The semiconductor device of claim 16 , wherein a top portion of the p-type source/drain epitaxial structure comprises fluorine residues.

19 . The semiconductor device of claim 16 , wherein the concentration of the p-type dopant species of the side portion of the topmost one of the semiconductor layers is greater than about 1E19 atoms/cm 3 .

20 . The semiconductor device of claim 16 , wherein the concentration of the p-type dopant species of the side portion of the second topmost one of the semiconductor layers is less than about 1E19 atoms/cm 3 .