SiC MOSFET with reduced on-resistance
A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.
1 . A method for forming a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the method comprises:
forming a gate dielectric that adjoins a body region arranged in a semiconductor body; and
forming a gate electrode on the gate dielectric, wherein forming the gate electrode comprises:
forming a first electrode layer;
implanting work function adjusting atoms into the first electrode layer; and
after implanting the work function adjusting atoms into the first electrode layer, forming a second electrode layer on the first electrode layer.
2 . The method of claim 1 ,
wherein the first electrode layer comprises at least one of a metal, a metal alloy, a metal nitride, or a metal carbide.
3 . The method of claim 1 ,
wherein the first electrode layer comprises a metal selected from the group consisting of titanium (Ti), molybdenum (Mo), and tantalum (Ta).
4 . The method of claim 1 ,
wherein the first electrode layer comprises a metal alloy selected from the group consisting of titanium aluminide (TiAl) and tungsten titanium (TiW).
5 . The method of claim 1 ,
wherein the first electrode layer comprises a metal nitride selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).
6 . The method of claim 1 ,
wherein the first electrode layer comprises titanium carbide (TIC).
7 . The method of claim 1 ,
wherein the first electrode layer is formed to have a thickness of between 5 nanometers and 100 nanometers.
8 . The method of claim 1 ,
wherein the implanted work function adjusting atoms comprise at least one of nitrogen (N) atoms or fluorine (F) atoms.
9 . The method of claim 1 ,
wherein an implantation dose of the work function adjusting atoms is:
between 1E14 centimeters −2 (cm −2 ) and 1E17 cm −2 .
10 . The method of claim 1 ,
wherein the second electrode layer comprises one of tungsten (W) or doped polysilicon.
11 . The method of claim 1 ,
wherein the method comprises forming the body region before forming the gate dielectric, and
wherein forming the body region comprises implanting dopant atoms via a first surface into the semiconductor body, and activating the implanted dopant atoms.
12 . The method of claim 11 ,
wherein an implantation dose of the dopant atoms is less than 1.3E13 centimeters −2 (cm −2 ).
13 . The method of claim 1 ,
wherein the gate dielectric and the gate electrode are formed in a trench of the semiconductor body,
wherein the gate dielectric and the first electrode layer are formed in the trench such that a residual trench remains, and
wherein the second electrode layer is formed such that the residual trench is filled.
14 . The method of claim 1 ,
wherein the gate dielectric and the gate electrode are formed above a first surface of the semiconductor body.
15 . The method of claim 1 ,
wherein forming the gate dielectric comprises depositing an oxide layer; and
wherein the method comprises performing an annealing process.
16 . The method of claim 15 ,
wherein the oxide layer comprises silicon oxide.
17 . The method of claim 1 ,
wherein forming the second electrode layer on the first electrode layer after implanting the work function adjusting atoms into the first electrode layer is associated with reducing an on-resistance of the SiC MOSFET without reducing a threshold voltage of the SiC MOSFET by more than a threshold amount.