Carbon-containing cap layer for doped semiconductor epitaxial layer
A semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having carrier dopants, and each cap epitaxial layer includes silicon and carbon un-doped with carrier dopants.
1 . A method of forming a doped semiconductor layer in a semiconductor structure, comprising:
performing a plurality of cycles of a first deposition process, a second deposition process subsequent to the first deposition process, and an etch process,
the first deposition process forming a doped semiconductor layer on an exposed surface of a substrate, the substrate comprising a semiconductor region and a dielectric region, wherein an epitaxial portion of the doped semiconductor layer is selectively formed on a surface of the semiconductor region, and an amorphous portion of the doped semiconductor layer is selectively formed on a surface of the dielectric region;
the second deposition process forming a cap layer on the doped semiconductor layer, wherein an epitaxial portion of the cap layer is selectively formed on a surface of the epitaxial portion of the doped semiconductor layer, and an amorphous portion of the cap layer is selectively formed on a surface of the amorphous portion of the doped semiconductor layer; and
the etch process selectively removing the amorphous portion of the cap layer and the amorphous portion of the doped semiconductor layer, and leaving the epitaxial portion of the cap layer and the epitaxial portion of the doped semiconductor layer, wherein
the doped semiconductor layer comprises silicon having carrier dopants, and
the cap layer comprises carbon not doped with carrier dopants.
2 . The method of claim 1 , wherein the carrier dopants comprise phosphorus.
3 . The method of claim 1 , wherein
the doped semiconductor layer has a thickness of between 15 Å and 20 Å, and
the cap layer has a thickness of between 5 Å and 15 Å.
4 . The method of claim 1 , wherein the first deposition process comprises flowing a silicon-containing precursor and a dopant source in a processing chamber.
5 . The method of claim 4 , wherein the second deposition process comprises flowing a silicon-containing precursor and a carbon source in the processing chamber.
6 . The method of claim 5 , wherein the etch process comprises flowing an etchant gas and a carrier gas in a processing gas, subsequent to the second deposition process.
7 . The method of claim 5 , the etch process comprises flowing an etchant gas and a carrier gas in a processing gas, simultaneously with the first deposition process and the second deposition process.
8 . The method of claim 5 , wherein the first deposition process and the second deposition process are performed at a low temperature less than about 450° C. and at a pressure of between 5 Torr and 600 Torr.
9 . A processing system, comprising:
a processing chamber; and
a system controller configured to cause the processing system to:
perform a plurality of cycles of a first deposition process, a second deposition process subsequent to the first deposition process, and an etch process,
the first deposition process forming a doped semiconductor layer on an exposed surface of a substrate, the substrate comprising a semiconductor region and a dielectric region, wherein an epitaxial portion of the doped semiconductor layer is selectively formed on a surface of the semiconductor region, and an amorphous portion of the doped semiconductor layer is selectively formed on a surface of the dielectric region;
the second deposition process forming a cap layer on the doped semiconductor layer, wherein an epitaxial portion of the cap layer is selectively formed on a surface of the epitaxial portion of the doped semiconductor layer, and an amorphous portion of the cap layer is selectively formed on a surface of the amorphous portion of the doped semiconductor layer; and
the etch process selectively removing the amorphous portion of the cap layer and the amorphous portion of the doped semiconductor layer, and leaving the epitaxial portion of the cap layer and the epitaxial portion of the doped semiconductor layer, wherein
the doped semiconductor layer comprises silicon having carrier dopants, and
the cap layer comprises carbon not doped with carrier dopants.
10 . The processing system of claim 9 , wherein the carrier dopants comprise phosphorus.
11 . The processing system of claim 9 , wherein
the doped semiconductor layer has a thickness of between 15 Å and 20 Å, and
the un-doped cap layer has a thickness of between 5 Å and 15 Å.
12 . The processing system of claim 9 , wherein the first deposition process comprises flowing a silicon-containing precursor and a dopant source in the processing chamber.
13 . The processing system of claim 12 , wherein the second deposition process comprises flowing a silicon-containing precursor and a carbon source in the processing chamber.
14 . The processing system of claim 13 , wherein the etch process comprises flowing an etchant gas and a carrier gas in a processing gas, subsequent to the second deposition process.
15 . The processing system of claim 13 , the etch process comprises flowing an etchant gas and a carrier gas in a processing gas, simultaneously with the first deposition process and the second deposition process.
16 . The processing system of claim 15 , wherein the first deposition process and the second deposition process are performed at a low temperature less than about 450° C. and at a pressure of between 5 Torr and 600 Torr.