Semiconductor device including extended backside contact structure

1 . A semiconductor device comprising:

a first source/drain region;

a first backside contact plug, at a back side of the semiconductor device, below the first source/drain region connected to the first backside contact plug; and

a shallow trench isolation (STI) structure extending around the first backside contact plug,

wherein the first backside contact plug comprises a first portion that is free of overlap with the first source/drain region in a first direction that is perpendicular to an upper surface of the STI structure,

wherein an uppermost surface of the STI structure is coplanar with an uppermost surface of the first backside contact plug,

wherein a lowermost surface of the STI structure is coplanar with a lowermost surface of the first backside contact plug, and

wherein the STI structure is free of interface therein.

2 . The semiconductor device of claim 1 , wherein the first portion of the first backside contact plug is free of overlap with the first source/drain region in at least one of a second direction and a third direction that intersects the second direction, and

wherein the second direction and the third direction are parallel with the upper surface of the STI structure.

3 . The semiconductor device of claim 1 , wherein the first backside contact plug further comprises a second portion that is free of overlap with the first source/drain region in the first direction,

wherein the second portion is opposite to the first portion in a a second direction or a third direction that intersects the second direction, and

wherein the second direction and the third direction are parallel with the upper surface of the STI structure.

4 . The semiconductor device of claim 1 , further comprising a backside isolation structure,

wherein the backside isolation structure comprises a first portion that is free of overlap with the first source/drain region in the first direction.

5 . The semiconductor device of claim 4 , wherein the first portion of the first backside contact plug extends into the first portion of the backside isolation structure.

6 . The semiconductor device of claim 5 , wherein the backside isolation structure is between the first backside contact plug and the STI structure in at least one of a second direction and a third direction that intersects the second direction, and

wherein the second direction and the third direction are parallel with the upper surface of the STI structure.

7 . The semiconductor device of claim 6 , wherein the STI structure is above the first portion of the first backside contact plug.

8 . The semiconductor device of claim 4 ,

wherein the backside isolation structure is between a first side surface of the first portion of the first backside contact plug and the STI structure,

wherein the backside isolation structure is on a second side surface of the first portion of the first backside contact plug,

wherein the first side surface of the first portion of the first backside contact plug extends in a second direction,

wherein the second side surface of the first portion of the first backside contact plug extends in a third direction that intersects the second direction, and

wherein the second direction and the third direction are parallel with the upper surface of the STI structure.

9 . The semiconductor device of claim 4 ,

wherein the first portion of the first backside contact plug faces the STI structure in a second direction without the backside isolation structure therebetween, and

wherein the second direction is parallel with the upper surface of the STI structure.

10 . The semiconductor device of claim 1 , wherein the first backside contact plug further comprises a second portion that overlaps the first source/drain region in the first direction,

wherein the first portion of the first backside contact plug is extended from the second portion of the first backside contact plug in a second direction,

wherein the first portion of the first backside contact plug has a first width in a third direction that is greater than a second width of the second portion of the first backside contact plug in the third direction that intersects the second direction, and

wherein the second direction and the third direction are parallel with the upper surface of the STI structure.

11 . The semiconductor device of claim 10 , wherein the second portion of the first backside contact plug has a third width in the third direction, and

wherein the third width is equal to the first width.

12 . The semiconductor device of claim 1 , further comprising:

a second backside contact plug, at the back side of the semiconductor device, below a second source/drain region connected to the second backside contact plug; and

a backside isolation structure between the second backside contact plug and the first backside contact plug,

wherein the second backside contact plug is entirely overlapped by the second source/drain region in the first direction.

13 . The semiconductor device of claim 12 , wherein the first backside contact plug further comprises a second portion that overlaps the first source/drain region in the first direction,

wherein the first portion of the first backside contact plug is extended from the second portion of the first backside contact plug in a second direction,

wherein the first portion of the first backside contact plug has a greater width than at least a first part of the second portion of the first backside contact plug in a third direction that intersects the second direction,

wherein the second direction and the third direction are parallel with the upper surface of the STI structure, and

wherein at least a second part of the second portion of the first backside contact plug has an equal width as the second backside contact plug in the third direction.

14 . The semiconductor device of claim 1 , further comprising backside metal lines, at the back side of the semiconductor device,

wherein at least one of the backside metal lines is connected to the first backside contact plug,

wherein the backside metal lines are arranged in a second direction and extend in a third direction, and

wherein the backside metal lines overlap the first backside contact plug in the first direction in a cross-section view in the second direction.

15 . A semiconductor device comprising:

a source/drain region;

a backside contact plug, at a back side of the semiconductor device, below the source/drain region connected to the backside contact plug, wherein the backside contact plug comprises an extended portion that is free of overlap with the source/drain region in a first direction;

backside metal lines at the back side of the semiconductor device; and

a shallow trench isolation (STI) structure extending around the backside contact plug,

wherein at least one of the backside metal lines is connected to the backside contact plug,

wherein the backside metal lines are arranged in a second direction and extend in a third direction,

wherein the backside metal lines overlap the backside contact plug in the first direction in a cross-section view in the second direction,

wherein the second direction intersects the third direction,

wherein the second direction and the third direction are parallel with an upper surface of the STI structure,

wherein the first direction is perpendicular to the upper surface of the STI structure,

wherein an uppermost surface of the backside contact plug is coplanar with an uppermost surface of the STI structure,

wherein a lowermost surface of the backside contact plug is coplanar with a lowermost surface of the STI structure, and

wherein the STI structure is a monolithic structure.

16 . The semiconductor device of claim 15 , wherein at least one of the backside metal lines overlaps the extended portion of the backside contact plug in the first direction.

17 . The semiconductor device of claim 16 , wherein the at least one of the metal lines is connected to the extended portion of the backside contact plug.

18 . A method of manufacturing a semiconductor device, the method comprising:

providing a transistor structure comprising a channel stack on a substrate;

forming a dummy pattern at a side surface the substrate such that the dummy pattern is free of overlap with the channel stack;

forming a first recess, in the substrate, below a space where a source/drain region is to be formed;

forming a source/drain region on the channel stack in the space above the first recess;

opening the first recess from a bottom thereof and removing the dummy pattern to form a second recess; and

filling the second recess with a backside contact plug connected to the source/drain region such that the backside contact plug comprises an extended portion, corresponding to the dummy pattern,

wherein the extended portion is free of overlap with the source/drain region in a first direction that is perpendicular to an upper surface of the substrate.

19 . The method of claim 18 , wherein the forming the dummy pattern comprises patterning the substrate to obtain the dummy pattern as a part of the substrate, and

wherein the dummy pattern and the substrate have a same material composition.

20 . The method of claim 19 , further comprising forming a placeholder structure in the first recess prior to the forming the source/drain region,

wherein the opening the first recess and removing the dummy pattern comprises:

removing the placeholder structure to obtain a third recess; and

extending the third recess by the removing the dummy pattern, thereby obtaining the second recess.