Semiconductor structure and method for manufacturing the same

1 . A semiconductor structure, comprising:

a substrate;

nanostructures over the substrate and spaced apart from each other in a Z-direction;

source/drain features electrically connected to and on opposite sides of the nanostructures in an X-direction;

a gate structure extending in a Y-direction and wrapping around the nanostructures; and

inner spacers between the nanostructures in the Z-direction, wherein each of the inner spacers comprises:

a soft core layer; and

a hard liner layer wrapping around the soft core layer.

2 . The semiconductor structure of claim 1 , wherein a Young's modulus of the hard liner layer is greater than a Young's modulus of the soft core layer.

3 . The semiconductor structure of claim 2 , wherein the soft core layer comprises low-k oxides, amorphous carbon, polymers, and air, and the hard liner layer comprises SiN, SiCN, SiO x , SiCO, and SiCON.

4 . The semiconductor structure of claim 1 , wherein a thickness of the soft core layer in the Z-direction is greater than a width of the soft core layer in the X-direction.

5 . The semiconductor structure of claim 4 , wherein the thickness of the soft core layer in the Z-direction is in a range from about 4 nm to about 7 nm and the width of the soft core layer in the X-direction is in a range from about 1 nm to about 3 nm.

6 . The semiconductor structure of claim 1 , wherein a thickness of the hard liner layers is in a range from about 0.5 nm to about 1.5 nm.

7 . The semiconductor structure of claim 6 , wherein the thickness of the hard liner layers in contact with the source/drain features in the X-direction is greater than the thickness of the hard liner layers in contact with the gate structure in the X-direction.

8 . The semiconductor structure of claim 1 , wherein a dimension of sidewalls of the hard liner layers in contact with the source/drain features in the Z-direction is greater than a dimension of sidewalls of the hard liner layers in contact with the gate structure in the Z-direction.

9 . The semiconductor structure of claim 1 , wherein each of the hard liner layers comprises a vertical sidewall in contact with the source/drain feature and a convex sidewall in contact with the gate structure.

10 . The semiconductor structure of claim 1 , wherein each of the hard liner layers comprises a concave sidewall in contact with the source/drain feature and a convex sidewall in contact with the gate structure.

11 . A semiconductor structure, comprising:

a substrate;

nanostructures over the substrate and spaced apart from each other in a Z-direction;

a gate structure extending in a Y-direction and wrapping around middle portions of the nanostructures;

source/drain features on opposite sides of the gate structure in an X-direction and attached to the nanostructures in the X-direction; and

inner spacers between side portions of the nanostructures in the Z-direction, wherein each of the inner spacers comprises:

a soft core layer; and

a hard liner layer wrapping around the soft core layer, wherein the hard liner layers separate the core layers from the nanostructures, the gate structure, and the source/drain features.

12 . The semiconductor structure of claim 11 , wherein a Young's modulus of the soft core layer is less than 0.8 times of a Young's modulus of the hard liner layer.

13 . The semiconductor structure of claim 11 , wherein a dielectric constant of the soft core layer is less than a dielectric constant of the hard liner layer, wherein the dielectric constant of the soft core layer is less than 3.9.

14 . The semiconductor structure of claim 13 , wherein each of the inner spacers has a rectangle shape in an X-Z cross-sectional view, wherein a thickness of the inner spacers in the Z-direction is greater than a width of the inner spacers in the X-direction.

15 . The semiconductor structure of claim 11 , wherein each of the inner spacers has a trapezoid shape in an X-Z cross-sectional view, wherein a dimension of sidewalls of the inner spacers in contact with the source/drain features in the Z-direction is greater than a dimension of sidewalls of the inner spacers in contact with the gate structure in the Z-direction.

16 . The semiconductor structure of claim 11 , wherein each of the inner spacers has a half ellipse shape in an X-Z cross-sectional view, wherein vertical sidewalls of the inner spacers are in contact with the source/drain features and convex sidewalls of the inner spacers are in contact with the gate structure.

17 . The semiconductor structure of claim 11 , wherein each of the inner spacers has a crescent shape in an X-Z cross-sectional view, wherein concave sidewalls of the inner spacers are in contact with the source/drain feature and convex sidewalls of the inner spacers are in contact with the gate structure.

18 . A method for manufacturing a semiconductor structure, comprising:

forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked in a Z-direction;

forming a dummy gate structure extending in a Y-direction and over the fin;

forming gate spacers on sidewalls of the dummy gate structure in an X-direction;

forming source/drain trenches in the fin and on opposite sides of the dummy gate structures in the X-direction;

removing side portions of the first semiconductor layers through the source/drain trenches to form gaps between the second semiconductor layers in the Z-direction and direct under the gate spacers;

forming first liner layers partially filling the gaps;

forming core layers partially filling spaces in the gaps and the first liner layers;

forming second liner layers filling remaining spaces in the gaps;

forming P-type source/drain features in the source/drain trenches; and

replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the second semiconductor layers.

19 . The method of claim 18 , further comprising:

forming first liner material partially filling the gaps and on sidewalls of the gate spacers and the second semiconductor layers;

trimming the first liner material to reduce thickness of the first liner material; and

removing the first liner material on sidewalls of the gate spacers and the second semiconductor layers to form the first liner layers.

20 . The method of claim 19 , further comprising:

forming core material filling the gaps and on sidewalls of the gate spacers and the second semiconductor layers;

removing the core material on sidewalls of the gate spacers and the second semiconductor layers and portions of the core material in the gaps to form the core layers;

forming second liner material filling the gaps and on sidewalls of the gate spacers and the second semiconductor layers; and

removing the second liner material on sidewalls of the gate spacers and the second semiconductor layers to form the second liner layers.