Power module including a semiconductor device with parasitic diode
A semiconductor device includes a substrate, an epitaxial layer on the substrate, a first well region in the epitaxial layer, a source region in the first well region, a source contact, a base region wrapping around a sidewall of the source contact and a second well region wrapping around the base region. The substrate, the epitaxial layer and the source region include a plurality of dopants of a first semiconductor type. A bottom of the source contact is lower than a bottom of the first well region. The base region and the second well region include a plurality of dopants of a second semiconductor type. The second semiconductor type is different from the first semiconductor type, and a doping concentration of the base region is higher than a doping concentration of the first well region and a doping concentration of the second well region.
1 . A semiconductor device, comprising:
a substrate;
an epitaxial layer on the substrate;
a first well region in the epitaxial layer;
a source region in the first well region, wherein the substrate, the epitaxial layer and the source region comprise a plurality of dopants of a first semiconductor type;
a source contact, wherein a bottom of the source contact is lower than a bottom of the first well region;
a base region wrapping around a sidewall of the source contact; and
a second well region wrapping around the base region, wherein the first well region, the base region and the second well region comprise a plurality of dopants of a second semiconductor type, the second semiconductor type is different from the first semiconductor type, and a doping concentration of the base region is higher than a doping concentration of the first well region and a doping concentration of the second well region, and the second well region is closer to the substrate than the first well region is.
2 . The semiconductor device of claim 1 , wherein a lower portion of the source contact and the source region are separated by the base region.
3 . The semiconductor device of claim 1 , wherein the base region and the source region are separated by the second well region.
4 . The semiconductor device of claim 1 , wherein a bottom of the base region is lower than the bottom of the first well region.