Method of manufacturing a three-dimensionally integrated structure having a clamping surface and a wafer stack with a chamfered surface
View Patent ↗A 3D integrated structure and a method for fabricating the structure. In the method, a first trimming process is performed in a peripheral region of a wafer stack to form a chamfered surface adjacent to and surrounding an active device region. As a result, a thickness of the wafer stack along the chamfered surface gradually decreases from an edge of the active device region outward. In this way, a photoresist layer can be subsequently easily applied to cover the junction of the active device region and the chamfered surface, without the formation of discontinuities there, which may affect the subsequent processes. Additionally, in the method, a second trimming process is performed at an edge of the peripheral region to form a clamping surface adjacent to and surrounding the chamfered surface. In this way, it is unnecessary to clamp the wafer stack at a top surface thereof.
1 . A method for fabricating a three-dimensionally integrated structure, comprising:
obtaining a wafer stack having a surface that includes an active device region and a peripheral region surrounding the active device region, wherein the wafer stack comprises at least three wafers;
forming a chamfered surface adjacent to and surrounding the active device region by performing a first trimming process in the peripheral region, wherein each wafer of the wafer stack comprises a sub-chamfered surface, wherein the sub-chamfered surface is a curved surface without angular transition, thereby allowing a smooth transition at an interface between the sub-chamfered surfaces of adjacent wafers; and
forming a clamping surface by performing a second trimming process at an edge of the peripheral region, wherein the clamping surface is for clamping the wafer stack and is adjacent to and surrounds the chamfered surface, wherein a thickness of the wafer stack along the chamfered surface gradually decreases from an edge of the active device region outward, and the thickness further decreases at the clamping surface.
2 . The method of claim 1 , wherein the curved surface is continuously differentiable.
3 . The method of claim 1 , wherein the clamping surface is a L-shaped clamping surface.
4 . The method of claim 1 , further comprising, after the formation of the clamping surface:
applying a photoresist layer onto the surface of the wafer stack, wherein the photoresist layer continuously covers the active device region and the chamfered surface;
forming a through opening in the photoresist layer in the active device region by exposing and developing the photoresist layer; and
forming a solder bump in the through opening.
5 . The method of claim 4 , wherein the solder bump is formed in the through opening by an electroplating process in which the wafer stack is clamped at the clamping surface by a clamp.
6 . The method of claim 4 , wherein a height difference between an edge of the chamfered surface and the clamping surface is smaller than a thickness of the photoresist layer.
7 . The method of claim 6 , wherein the height difference is greater than 0, and smaller than or equal to 60 μm.