Bonding layer between stacked integrated circuits
A semiconductor assembly including: a first semiconductor having a plurality of electrical contacts extending from an upper surface of the first semiconductor; a second semiconductor adjacent to the first semiconductor; and a mesh disposed between and affixed to the upper surface of the first semiconductor and the lower surface of the second semiconductor. A lower surface of the second semiconductor is electrically connected to the first semiconductor via the plurality of electrical contacts. The mesh comprises a plurality of interconnecting struts defining a plurality of openings, wherein the plurality of openings is configured to receive the plurality of electrical contacts.
1 . A stacked semiconductor assembly comprising:
a first semiconductor having a plurality of electrical contacts extending from an upper surface of the first semiconductor;
a second semiconductor adjacent to the first semiconductor, wherein a lower surface of the second semiconductor is electrically connected to the first semiconductor via the plurality of electrical contacts; and
a mesh disposed between and affixed to the upper surface of the first semiconductor and the lower surface of the second semiconductor, wherein the mesh comprises a plurality of interconnecting struts defining a plurality of openings, and wherein the plurality of openings is configured to receive the plurality of electrical contacts,
wherein the mesh is configured to affix the first semiconductor to the second semiconductor.
2 . The stacked semiconductor assembly of claim 1 , wherein the mesh forms a hermetic seal with the upper surface of the first semiconductor and with the lower surface of the second semiconductor around each opening of the plurality of openings.
3 . The stacked semiconductor assembly of claim 1 , wherein each electrical contact of the plurality of electrical contacts comprises a microbump.
4 . The stacked semiconductor assembly of claim 1 , wherein at least one of the first semiconductor or the second semiconductor comprises an application specific integrated circuit (ASIC).
5 . The stacked semiconductor assembly of claim 1 , wherein at least one of the first semiconductor or the second semiconductor comprises a commercial off-the-shelf (COTS) semiconductor.
6 . The stacked semiconductor assembly of claim 1 , wherein the plurality of interconnecting struts comprises a solder material.
7 . The stacked semiconductor assembly of claim 1 , wherein the mesh is configured to distribute thermal energy along the plurality of interconnecting struts.
8 . The stacked semiconductor assembly of claim 1 , wherein the mesh distributes electrical signals along the plurality of interconnecting struts and between the first semiconductor and the second semiconductor.
9 . The stacked semiconductor assembly of claim 1 , wherein each of the plurality of openings of the mesh defines an adjustable diameter.
10 . The stacked semiconductor assembly of claim 1 , wherein the mesh comprises a first mesh, wherein the plurality of electrical contacts comprises a first plurality of electrical contacts, wherein the plurality of openings comprises a first plurality of openings, wherein the plurality of interconnecting struts comprises a first plurality of interconnecting struts, and wherein the stacked semiconductor assembly further comprises:
a third semiconductor adjacent to the second semiconductor, wherein a lower surface of the third semiconductor is electrically connected to an upper surface of the second semiconductor via a second plurality of electrical contacts extending from the lower surface of the third semiconductor; and
a second mesh disposed between and affixed to the upper surface of the second semiconductor and the lower surface of the third semiconductor, wherein the second mesh comprises a plurality of second interconnecting struts defining a plurality of second openings configured to receive the second plurality of electrical contacts.
11 . The stacked semiconductor assembly of claim 1 , wherein the mesh and the plurality of electrical contacts define a bonding layer between the first semiconductor and the second semiconductor.
12 . A semiconductor mesh interface comprising:
an adhesive material comprising a plurality of interconnecting struts defining a plurality of openings extending from a first surface of the adhesive material to a second surface of the adhesive material,
wherein the first surface of the adhesive material is configured to be affixed to an upper surface of a first semiconductor,
wherein the second surface of the adhesive material is configured to be affixed to a lower surface of a second semiconductor,
wherein one or more of the plurality of openings is configured to receive electrical contacts extending between the first semiconductor and the second semiconductor, and
wherein the adhesive material is configured to affix the first semiconductor to the second semiconductor.
13 . The semiconductor mesh interface of claim 12 , wherein the first surface of the adhesive material is configured to form a first hermetic seal with the upper surface of the first semiconductor around a first end of a first opening of the plurality of openings, and wherein the second surface of the adhesive material is configured to form a second hermetic seal with the lower surface of the second semiconductor around a second end of the first opening of the plurality of openings.
14 . The semiconductor mesh interface of claim 12 , wherein the adhesive material comprises a solder material.
15 . The semiconductor mesh interface of claim 12 , wherein the adhesive material is configured to distribute thermal energy along the plurality of interconnecting struts and throughout a volume of the adhesive material.
16 . The semiconductor mesh interface of claim 12 , wherein the adhesive material is configured to transmit electrical signals from a first location on the upper surface of the first semiconductor to a second location on the lower surface of the second semiconductor via the plurality of interconnecting struts.
17 . A method comprising:
disposing a mesh over a first surface of a first semiconductor, wherein the mesh comprises:
an adhesive material comprising a plurality of interconnecting struts defining a plurality of openings,
wherein when the mesh is disposed over the first surface of the first semiconductor, the plurality of openings is configured to receive a first plurality of electrical contacts extending from the first surface of the first semiconductor;
aligning a second plurality of electrical contacts extending from a second surface of a second semiconductor with the first plurality of electrical contacts of the first semiconductor;
electrically connecting the first semiconductor with the second semiconductor via the first plurality of electrical contacts and the second plurality of electrical contacts; and
affixing a first surface of the mesh to the first surface of the first semiconductor and a second surface of the mesh to the second surface of the second semiconductor.
18 . The method of claim 17 , wherein the adhesive material comprises a solder material.
19 . The method of claim 17 , wherein one or more of the first plurality of electrical contacts and the second plurality of electrical contacts comprises microbumps.
20 . The method of claim 17 , wherein:
affixing the first surface of the mesh to the first surface of the first semiconductor comprises forming a first hermetic seal between the first surface of the mesh and the first surface of the first semiconductor around a first end of a first opening of the plurality of openings; and
affixing the second surface of the mesh to the second surface of the second semiconductor comprises forming a second hermetic seal between the second surface of the mesh and the second surface of the second semiconductor around a second end of the first opening of the plurality of openings.