Method of forming semiconductor device
A method includes a number of operations. A bottom transistor and a top transistor overlapping the bottom transistor are formed. A vertical local interconnect (VLI) structure is formed and electrically connects source/drain regions of the bottom transistor and the top transistor. A hard mask layer is formed over the VLI structure, wherein the hard mask layer includes a bottom nitride layer, a top nitride layer and an amorphous semiconductive layer directly between the bottom nitride layer and the top nitride layer. The hard mask layer is patterned. A trench is formed in the VLI structure. An isolation structure is formed in the trench. A first polishing process is performed to the isolation structure and the hard mask layer, wherein the first polishing process stops the amorphous semiconductive layer. A second polish process is performed to the isolation structure, the bottom nitride layer and the amorphous semiconductive layer.
1 . A method comprising:
forming a bottom transistor and a top transistor overlapping the bottom transistor;
forming a vertical local interconnect (VLI) structure electrically connecting a source/drain region of the bottom transistor and a source/drain region of the top transistor;
forming a hard mask layer over the VLI structure, wherein the hard mask layer comprises a bottom nitride layer, a top nitride layer and an amorphous semiconductive layer directly between the bottom nitride layer and the top nitride layer;
patterning the hard mask layer;
forming a trench in the VLI structure;
forming an isolation structure in the trench;
performing a first polishing process to the isolation structure and the hard mask layer, wherein the first polishing process stops the amorphous semiconductive layer; and
performing a second polish process to the isolation structure, the bottom nitride layer and the amorphous semiconductive layer.
2 . The method of claim 1 , wherein before the first polishing process is performed, a thickness of the isolation structure and the top nitride layer higher than the amorphous semiconductive layer is greater than a thickness of the amorphous semiconductive layer and the bottom nitride layer.
3 . The method of claim 1 , wherein the first polishing process polishes the top nitride layer at a first polish rate, and polishes the amorphous semiconductive layer at second polish rate, and the first polish rate is different from the second polish rate.
4 . The method of claim 1 , wherein the top nitride layer and the bottom nitride layer comprise silicon nitride.
5 . The method of claim 1 , wherein the amorphous semiconductive layer comprises amorphous semiconductive silicon.
6 . The method of claim 1 , wherein forming the hard mask layer further comprises forming an oxide layer over the top nitride layer.
7 . The method of claim 6 , wherein a thickness of the oxide layer is greater than a thickness of any of the top nitride layer, the amorphous semiconductive layer and the bottom nitride layer after the hard mask layer is formed.
8 . The method of claim 6 , wherein the isolation structure is formed and extends from a top surface of the oxide layer into the trench before the first polish process is performed.
9 . The method of claim 1 , wherein forming the isolation structure comprises forming a liner through the amorphous semiconductive layer of the hard mask layer and in the trench of the VLI structure.
10 . The method of claim 1 , wherein the first polishing process has a first polish selectivity between the top nitride layer and the amorphous semiconductive layer, the second polishing process has a second polish selectivity between the bottom nitride layer and the amorphous semiconductive layer, and the second polish selectivity is less than the first polish selectivity.
11 . A method, comprising:
forming a first transistor and a second transistor over the first transistor;
forming a first hard mask layer over the second transistor, wherein the first hard mask layer comprises a bottom nitride layer, a top nitride layer and an amorphous semiconductive layer directly between the bottom nitride layer and the top nitride layer;
patterning the first hard mask layer;
forming a first trench extending through gate structures of the first transistor and the second transistor;
forming a vertical local interconnect (VLI) structure in the first trench, the VLI structure electrically connecting a source/drain region of the first transistor to a source/drain region of the second transistor;
performing a first polishing process to the VLI structure and the first hard mask layer, wherein the first polishing process stops at a level of the amorphous semiconductive layer; and
after the first polishing process stops, performing a second polish process to the VLI structure, the bottom nitride layer and the amorphous semiconductive layer.
12 . The method of claim 11 , wherein a thickness of the top nitride layer is greater than a thickness of the amorphous semiconductive layer and the bottom nitride layer.
13 . The method of claim 11 , wherein the top nitride layer and the bottom nitride layer comprise silicon nitride.
14 . The method of claim 11 , wherein the amorphous semiconductive layer comprises amorphous semiconductive silicon.
15 . The method of claim 11 , wherein forming the VLI structure comprises forming a nitride liner through the top nitride layer, the amorphous semiconductive layer and the bottom nitride layer of the first hard mask layer.
16 . The method of claim 11 , further comprising:
forming a second hard mask layer over the VLI structure, wherein the second hard mask layer comprises a bottom nitride layer, a top nitride layer and an amorphous semiconductive layer directly between the bottom nitride layer and the top nitride layer;
patterning the second hard mask layer;
forming a second trench in the VLI structure;
forming an isolation structure in the second trench; and
performing a third polishing process to the isolation structure and the second hard mask layer.
17 . A method comprising:
forming a first transistor and a second transistor, wherein the second transistor overlaps the first transistor;
forming a hard mask layer over the second transistor, comprising:
forming a bottom mask layer;
forming an oxygen-free polish stop layer over the bottom mask layer;
forming a protective layer over the oxygen-free polish stop layer; and
forming an oxide layer over the protective layer;
patterning the hard mask layer;
forming a trench in gate structures of the first and second transistors;
forming an oxygen-free liner in the trench;
forming an oxide insulating layer over the oxygen-free liner; and
performing a polishing process to the hard mask, the oxygen-free liner and the oxide insulating layer, wherein the polishing process stops at a level of the oxygen-free polish stop layer.
18 . The method of claim 17 , wherein the hard mask layer comprises an oxide-free material.
19 . The method of claim 17 , wherein the polish process has a first polish rate on the protective layer and a second polish rate on the oxygen-free polish stop layer, the first polish rate is different from the second polish rate.
20 . The method of claim 17 , wherein the oxygen-free polish stop layer comprises amorphous silicon.