Fin loss prevention
The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
1 . A semiconductor device, comprising:
a substrate;
a first structure, comprising:
a first semiconductor layer of a first material disposed on the substrate, and
a first crystalline semiconductor layer disposed on the first semiconductor layer;
a second structure, comprising:
a second semiconductor layer of a second material disposed on the substrate, and
a second crystalline semiconductor layer disposed on the second semiconductor layer;
an isolation structure disposed between the first and second structures, wherein a top surface of the isolation structure and bottom surfaces of the first and second semiconductor layers are on a surface plane; and
a gate structure disposed on the first and second structures and on the isolation structure.
2 . The semiconductor device of claim 1 , wherein the first semiconductor layer comprises a silicon layer.
3 . The semiconductor device of claim 1 , wherein the second semiconductor layer comprises a silicon germanium layer.
4 . The semiconductor device of claim 1 , wherein each of the first and second crystalline semiconductor layers comprises a crystalline silicon layer.
5 . The semiconductor device of claim 1 , wherein a thickness of the first semiconductor layer is greater than a thickness of the first crystalline semiconductor layer.
6 . The semiconductor device of claim 1 , wherein the gate structure comprises a gate electrode layer disposed on the first and second structures and on the isolation structure.
7 . The semiconductor device of claim 1 , wherein the gate structure comprises:
a first gate dielectric layer disposed on the first semiconductor layer and on the first crystalline semiconductor layer; and
a second gate dielectric layer disposed on the second semiconductor layer and on the second crystalline semiconductor layer.
8 . The semiconductor device of claim 1 , wherein the gate structure comprises a gate dielectric layer disposed on a top surface and sidewalls of the first crystalline semiconductor layer.
9 . The semiconductor device of claim 1 , further comprising a liner disposed along sidewalls of the isolation structure, wherein a top surface of the liner is in contact with a bottom surface of the gate structure.
10 . The semiconductor device of claim 1 , wherein the first structure further comprises a p-type doped region under the first semiconductor layer; and
wherein a top surface of the p-type doped region and the top surface of the isolation structure are on the surface plane.
11 . A semiconductor device, comprising:
a substrate;
a fin structure, comprising:
a first fin portion comprising a doped region disposed on the substrate;
a second fin portion comprising a first semiconductor layer disposed on the first fin portion, and
a third fin portion comprising a second semiconductor layer disposed on the second fin portion; and
a gate structure disposed on the fin structure, wherein a bottom surface of the gate structure, a top surface of the first fin portion, and a bottom surface of the second fin portion are on a surface plane.
12 . The semiconductor device of claim 11 , further comprising a liner disposed along sidewalls of the first fin portion, wherein a top surface of the liner is on the surface plane.
13 . The semiconductor device of claim 11 , wherein the first semiconductor layer comprises a silicon layer.
14 . The semiconductor device of claim 11 , wherein the first semiconductor layer comprises a silicon germanium layer.
15 . The semiconductor device of claim 11 , wherein the second semiconductor layer comprises a crystalline silicon layer.
16 . The semiconductor device of claim 11 , wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer.
17 . A semiconductor device, comprising:
a substrate;
a first fin structure, comprising:
a silicon-based fin portion disposed on the substrate; and
a first crystalline semiconductor layer disposed on the silicon-based fin portion;
a second fin structure, comprising:
a silicon-germanium-based fin portion disposed on the substrate; and
a second crystalline semiconductor layer disposed on the silicon-germanium-based fin portion; and
a gate structure disposed on the first and second fin structures, wherein a bottom surface of the gate structure, a bottom surface of the silicon-based fin portion, and a bottom surface of the silicon-germanium-based fin portion are on a same surface plane.
18 . The semiconductor device of claim 17 , wherein each of the first and second crystalline semiconductor layers comprises a crystalline silicon layer.
19 . The semiconductor device of claim 17 , wherein each of the first and second crystalline semiconductor layers comprises a crystalline silicon layer with a top surface parallel to a (100) crystal plane.
20 . The semiconductor device of claim 17 , wherein the gate structure comprises a gate dielectric layer disposed on top surfaces and sidewalls of the first and second crystalline semiconductor layers.