Power semiconductor device comprising a wide bandgap substrate

1 . A power device comprising:

a substrate comprising a p-doped SiC material, the substrate comprising a first surface and a second surface opposite the first surface;

a high voltage heterojunction transistor formed over the first surface of the substrate, the high voltage heterojunction transistor comprising:

a III-nitride semiconductor region comprising a heterojunction formed between a GaN layer and an AlGaN layer;

a drain terminal operatively connected to the III-nitride semiconductor region;

a source terminal laterally spaced from the drain terminal and operatively connected to the III-nitride semiconductor region; and

a gate terminal positioned over the III-nitride semiconductor region, the gate terminal being formed between the drain terminal and the source terminal;

a high voltage diode comprising:

a first p-doped region with a first doping density, the first p-doped region associated with the substrate,

a second p-doped region with a second doping density, wherein the second doping density is less than the first doping density, the second p-doped region positioned between the first p-doped region and the first surface and forming a drift region for the high voltage diode such that at least part of the drift region is directly under and in physical contact with the high voltage heterojunction transistor; and

an anode terminal operatively connected to the second surface of the substrate and to the source terminal; and

a cathode terminal operatively connected to the first surface of the substrate and to the drain terminal.

2 . The power device according to claim 1 , wherein the power device is configured such that when a higher voltage is applied between the drain terminal with respect to the source terminal of the heterojunction transistor, the high voltage diode is in a reverse bias mode thereby blocking a substantial fraction of an applied voltage within the drift region.

3 . The power device according to claim 1 , wherein

the power device is configured such that, when a high voltage is applied across the drain and source terminals, the high voltage diode is reverse biased and supports a large depletion layer within the doped region; and

wherein at least part of the depletion layer is formed below an active region, wherein the depletion layer is configured to contribute to supporting a voltage between the drain terminal of the heterojunction transistor and an anode terminal of the high voltage diode.

4 . The power device according to claim 1 , wherein the substrate comprises:

a n-doped region operatively connected to a cathode terminal.

5 . The power device according to claim 4 , wherein the n-doped region has a third doping density that is greater than the second doping density.

6 . The power device according to claim 4 , wherein the cathode terminal at least partially extends into the substrate from the first surface, and wherein the n-doped region is positioned to surround the cathode terminal within the substrate.

7 . The power device according to claim 1 , wherein a cathode forms at least in part a Schottky contact to the substrate.

8 . The power device according to claim 7 , wherein the high voltage diode is a Schottky diode, and wherein the Schottky contact is positioned between adjacent highly doped n-type regions.

9 . The power device according to claim 1 , wherein

the high voltage diode is configured as an anti-parallel diode for the heterojunction transistor, the high voltage diode further being configured to become forward-biased when the heterojunction transistor operates in a reverse conduction mode.

10 . The power device according to claim 9 , wherein the anti-parallel diode is configured to provide an extra current path during the reverse conduction mode of the heterojunction transistor, either as a main anti-parallel diode, as a surge diode, or as a diode in parallel with an intrinsic reverse conduction structure of the heterojunction transistor.

11 . The power device according to claim 1 , where the heterojunction comprises at least one active two dimensional carrier gas channel.

12 . The power device according to claim 1 , further comprising a second heterojunction transistor positioned over the substrate, the second heterojunction transistor comprising:

a second active region comprising a second heterojunction formed between a second GaN layer and a second AlGaN layer;

a second drain terminal operatively connected to the second active region;

a second source terminal laterally spaced from the second drain terminal and operatively connected to the second active region; and

a second gate terminal positioned over the second active region, the second gate terminal being formed between the second drain terminal and the second source terminal.

13 . The power device according to claim 1 , comprising one or more integrated low-voltage devices or circuits, the low-voltage circuits positioned either:

(i) adjacent to the heterojunction transistor;

(ii) in the substrate adjacent to the heterojunction transistor; or

(iii) adjacent to the high voltage diode.

14 . The power device according to claim 1 , wherein the substrate comprises a superjunction structure formed of laterally or vertically alternating n and p doped layers positioned between the first and second p-doped regions, the superjunction structure positioned below at least part of the heterojunction transistor.

15 . The power device according to claim 1 , wherein at least a cathode terminal is operatively connected to a fixed high voltage rail, or an anode terminal is operatively connected to a low voltage DC terminal.