Semiconductor device
A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Log e (L 2 /SD), the dispersion degree is not less than 2 and not more than 15.
1 . A semiconductor device comprising:
a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region;
an IGBT region that is provided on the first main surface; and
a diode region that is provided outside the IGBT region on the first main surface;
an insulating layer selectively covering the IGBT region and the diode region on the first main surface; and
an emitter terminal covering the insulating layer and having a portion directly contacting with the diode region, wherein
the insulating layer has a diode opening exposing the diode region; and
an angle that an inner wall of the diode opening forms with the first main surface inside the insulating layer is not less than 45° and less than 90°,
the IGBT region includes a gate structure of a trench electrode type provided on the first main surface,
the diode region includes a plurality of anode regions and a plurality of separating structures of a trench electrode type are provided on the first main surface,
the diode opening exposes the plurality of anode regions and the plurality of separating structures, and
the emitter terminal is directly connected to at least one anode region of the plurality of anode regions and at least one separating structure of the plurality of separating structures.
2 . The semiconductor device according to claim 1 , wherein
the diode region includes an anode region of a p-type provided at a surface layer portion of the first main surface, and
the emitter terminal is electrically connected to the anode region.
3 . The semiconductor device according to claim 1 , wherein
the gate structure has a depth of not less than 4 μm and not more than 5 μm, not less than 5 μm and not more than 6 μm, or not less than 6 μm and not more than 7 μm, and
the plurality of separating structures each have a depth of not less than 4 μm and not more than 5 μm, not less than 5 μm and not more than 6 μm, or not less than 6 μm and not more than 7 μm.
4 . The semiconductor device according to claim 1 , wherein
the gate structure has a width of not less than 0.5 μm and not more than 1 μm, or not less than 1 μm and not more than 1.5 μm, and
the plurality of separating structures each have a width of not less than 0.5 μm and not more than 1 μm, or not less than 1 μm and not more than 1.5 μm.
5 . The semiconductor device according to claim 1 , wherein the plurality of separating structures each have a depth equal to a depth of the gate structure.
6 . The semiconductor device according to claim 1 , wherein the plurality of separating structures each have a width equal to a width of the gate structure.
7 . The semiconductor device according to claim 1 , wherein
the IGBT region includes a plurality of gate structures provided at intervals from each other on the first main surface, and
the diode region includes the plurality of separating structures provided at intervals from each other on the first main surface.
8 . The semiconductor device according to claim 7 , wherein
the IGBT region includes a collector region of a p-type provided at a surface layer portion of the second main surface and opposing the plurality of gate structures in a thickness direction of the semiconductor layer, and
the diode region includes a cathode region of an n-type provided at a surface layer portion of the second main surface and opposing the plurality of separating structures in the thickness direction of the semiconductor layer.
9 . The semiconductor device according to claim 8 , wherein
the plurality of separating structures include an outermost separating structure adjacent to the IGBT region, and
the cathode region has a portion opposing the outermost separating structure in the thickness direction of the semiconductor layer.
10 . The semiconductor device according to claim 1 , wherein the IGBT region includes a body region of a p-type provided at a surface layer portion of the first main surface along the gate structure, and an emitter region of an n-type provided at a surface layer portion of the body region along the gate structure.
11 . The semiconductor device according to claim 10 , wherein the body region is spaced from a depth position of a middle portion of the gate structure to the first main surface side.
12 . The semiconductor device according to claim 1 , wherein
a plurality of IGBT regions is provided at intervals from each other on the first main surface, and
the diode region is provided in a region between the plurality of IGBT regions on the first main surface.
13 . The semiconductor device according to claim 12 , wherein a plurality of diode regions is provided at intervals from each other on the first main surface.
14 . The semiconductor device according to claim 13 , wherein the plurality of the diode regions and the plurality of IGBT regions are arrayed alternately.
15 . The semiconductor device according to claim 13 , wherein a second ratio that a total area of the plurality of diode regions occupies in an area of the active region in plan view is not more than a first ratio that a total area of the plurality of IGBT regions occupies in the area of the active region in plan view.
16 . The semiconductor device according to claim 1 , further comprising a temperature sensor provided on the first main surface.
17 . The semiconductor device according to claim 1 , further comprising a gate terminal spaced from the emitter terminal and placed on the insulating layer.
18 . The semiconductor device according to claim 1 , further comprising a collector terminal covering the second main surface.