Epitaxial source/drain structures for multigate devices and methods of fabricating thereof

1 . A semiconductor structure comprising:

a semiconductor substrate;

a first channel stack, a first gate over the first channel stack, and a first epitaxial source/drain structure adjacent to the first channel stack, wherein the first channel stack, the first gate, and the first epitaxial source/drain structure are over the semiconductor substrate, and further wherein the first epitaxial source/drain structure includes:

a first undoped semiconductor layer, and

a first doped semiconductor layer over the first undoped semiconductor layer, wherein the first undoped semiconductor layer is between the first doped semiconductor layer and the semiconductor substrate;

a second channel stack, a second gate over the second channel stack, and a second epitaxial source/drain structure adjacent to the second channel stack, wherein the second channel stack, the second gate, and the second epitaxial source/drain structure are over the semiconductor substrate, and further wherein the second epitaxial source/drain structure includes:

a second undoped semiconductor layer, and

a second doped semiconductor layer over the second undoped semiconductor layer, wherein the second undoped semiconductor layer is between the second doped semiconductor layer and the semiconductor substrate;

wherein the first undoped semiconductor layer extends a first depth into the semiconductor substrate, the second undoped semiconductor layer extends a second depth into the semiconductor substrate, and the second depth is different than the first depth;

wherein the first channel stack has a first channel length and a height, the second channel stack has a second channel length and the height, and the second channel length is different than the first channel length; and

wherein the first depth and the second depth are configured relative to the height based on the first channel length and the second channel length, respectively, wherein the first depth is less than the height if the first channel length is less than 20 nm, the first depth is greater than the height if the first channel length is greater than 20 nm, the second depth is less than the height if the second channel length is less than 20 nm, and the second depth is greater than the height if the second channel length is greater than 20 nm.

2 . The semiconductor structure of claim 1 , wherein the first depth is greater than the second depth, the first depth is greater than the height, the second depth is less than the height, and the first channel length is greater than the second channel length.

3 . The semiconductor structure of claim 1 , wherein a first configuration of the first undoped semiconductor layer and the first doped semiconductor layer in the first epitaxial source/drain structure is different than a second configuration of the second undoped semiconductor layer and the second doped semiconductor layer in the second epitaxial source/drain structure.

4 . The semiconductor structure of claim 1 , wherein a first ratio of the height to the first depth is greater than one, a second ratio of the height to the second depth is less than one, the first depth is less than the second depth, and the first channel length is less than the second channel length.

5 . The semiconductor structure of claim 1 , wherein the first epitaxial source/drain structure has a first width, the second epitaxial source/drain structure has a second width, and the first width is different than the second width.

6 . The semiconductor structure of claim 1 , wherein a first ratio of the height to the first depth is 1 to 4 if the first channel length is less than 20 nm, the first ratio of the height to the first depth is 0.5 to 0.9 if the first channel length is greater than 20 nm, a second ratio of the height to the second depth is 1 to 4 if the second channel length is less than 20 nm, and the second ratio of the height to the second depth is 0.5 to 0.9 if the second channel length is greater than 20 nm.

7 . The semiconductor structure of claim 1 , wherein:

the first doped semiconductor layer has a first thickness that is greater than the height, such that the first doped semiconductor layer extends a third depth into the semiconductor substrate, wherein the third depth is less than the first depth and the second depth;

the second doped semiconductor layer has a second thickness that is greater than the height, such that the second doped semiconductor layer extends a fourth depth into the semiconductor substrate, wherein the fourth depth is different than the third depth and the third depth is less than the first depth and the second depth; and

the third depth and the fourth depth depend on the first channel length and the second channel length, respectively.

8 . The semiconductor structure of claim 1 , wherein:

the first epitaxial source/drain structure further includes a third doped semiconductor layer over the first doped semiconductor layer and a fourth doped semiconductor layer over the third doped semiconductor layer, wherein the first doped semiconductor layer is between the first channel stack and the third doped semiconductor layer; and

the second epitaxial source/drain structure further includes a fifth doped semiconductor layer over the second doped semiconductor layer and a sixth doped semiconductor layer over the fifth doped semiconductor layer, wherein the second doped semiconductor layer is between the second channel stack and the fifth doped semiconductor layer.

9 . A device comprising:

a first transistor having a first channel layer, a first gate surrounding the first channel layer, and a first epitaxial source/drain structure disposed adjacent to the first channel layer, wherein the first channel layer, the first gate, and the first epitaxial source/drain structure are disposed over a semiconductor substrate and the first epitaxial source/drain structure includes:

a first undoped epitaxial layer with a first trough-shaped top surface, such that the first undoped epitaxial layer forms a first trough, and

a first doped epitaxial layer that fills the first trough of the first undoped epitaxial layer, the first doped epitaxial layer having a first inner portion having a first dopant concentration and a first outer portion having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration and the first outer portion of the first doped epitaxial layer is disposed between the first undoped epitaxial layer and the first inner portion of the first doped epitaxial layer; and

a second transistor having a second channel layer, a second gate surrounding the second channel layer, and a second epitaxial source/drain structure disposed adjacent to the second channel layer, wherein the second channel layer, the second gate, and the second epitaxial source/drain structure are disposed over the semiconductor substrate and the second epitaxial source/drain structure includes:

a second undoped epitaxial layer with a second trough-shaped top surface such that the second undoped epitaxial layer forms a second trough, wherein;

the second trough-shaped top surface is configured different than the first trough-shaped top surface, the first trough-shaped top surface is configured based on a first active region size corresponding with the first transistor, the second trough-shaped top surface is configured based on a second active region size corresponding with the second transistor, the first active region size is greater than 30 nm, and the second active region size is less than 30 nm;

the first undoped epitaxial layer has a first minimum thickness, the first trough-shaped top surface has a first depth, the second undoped epitaxial layer has a second minimum thickness, and the second trough-shaped top surface has a second depth; and

a first ratio of the first depth to the first minimum thickness is 0.1 to 0.5 and a second ratio of the second depth to the second minimum thickness is 0.05 to 0.3, and

a second doped epitaxial layer that fills the second trough of the second undoped epitaxial layer, the second doped epitaxial layer having a second inner portion having the first dopant concentration and a second outer portion having the second dopant concentration, wherein the second outer portion of the second doped epitaxial layer is disposed between the second undoped epitaxial layer and the second inner portion of the second doped epitaxial layer.

10 . The device of claim 9 , wherein a first lowest point of the first trough-shaped top surface of the first undoped epitaxial layer relative to a topmost surface of the semiconductor substrate is different than a second lowest point of the second trough-shaped top surface of the second undoped epitaxial layer relative to the topmost surface of the semiconductor substrate.

11 . The device of claim 9 , wherein the first undoped epitaxial layer and the second undoped epitaxial layer are each positioned below a topmost surface of the semiconductor substrate.

12 . The device of claim 9 , wherein the first channel layer has a first length, the second channel layer has a second length, and the second length is different than the first length.

13 . The device of claim 9 , wherein the first undoped epitaxial layer has a first central portion disposed between first end portions, the second undoped epitaxial layer has a second central portion disposed between second end portions, the first central portion and the second central portion have different profiles, and the first end portions and the second end portions have different profiles.

14 . The device of claim 9 , wherein a first distance between a bottommost point of the first outer portion of the first doped epitaxial layer and a bottommost surface of the first epitaxial source/drain structure is different than a second distance between a bottommost point of the second outer portion of the second doped epitaxial layer and a bottommost surface of the second epitaxial source/drain structure.

15 . The device of claim 9 , wherein:

the first epitaxial source/drain structure further includes a third doped epitaxial layer disposed over the first outer portion of the first doped epitaxial layer;

the second epitaxial source/drain structure further includes a fourth doped epitaxial layer disposed over the second outer portion of the second doped epitaxial layer; and

wherein the third doped epitaxial layer has a first thickness and the fourth doped epitaxial layer has a second thickness different than the first thickness.

16 . A semiconductor structure comprising:

a first semiconductor layer extending between first source/drain structures, wherein the first semiconductor layer is disposed over a first semiconductor mesa and at least one of the first source/drain structures includes:

a first undoped semiconductor layer, and

a first doped semiconductor layer over the first undoped semiconductor layer, wherein the first undoped semiconductor layer is between the first doped semiconductor layer and the first semiconductor mesa;

a second semiconductor layer extending between second source/drain structures, wherein the second semiconductor layer is disposed over a second semiconductor mesa and at least one of the second source/drain structures includes:

a second undoped semiconductor layer, and

a second doped semiconductor layer over the second undoped semiconductor layer, wherein the second undoped semiconductor layer is between the second doped semiconductor layer and the second semiconductor mesa;

wherein a first distance is between a bottom of the first undoped semiconductor layer and a top of the first semiconductor mesa, a second distance is between a bottom of the second undoped semiconductor layer and a top of the second semiconductor mesa, and the second distance is greater than the first distance;

wherein a third distance is between a top of the first semiconductor layer and the top of the first semiconductor mesa, a fourth distance is between a top of the second semiconductor layer and the top of the second semiconductor mesa, the third distance is less than the first distance, and the fourth distance is greater than the second distance;

wherein the first semiconductor layer has a first length between the first source/drain structures, the second semiconductor layer has a second length between the second source/drain structures, and the second length is greater than the first length; and

wherein a first ratio of the third distance to the first distance is at least 1 and a second ratio of the fourth distance to the second distance is less than 1.

17 . The semiconductor structure of claim 16 , wherein:

the first undoped semiconductor layer has a first top concave surface;

the second undoped semiconductor layer has a second top concave surface; and

a fifth distance is between a bottom of the first concave top surface and the top of the first semiconductor mesa, a sixth distance is between a bottom of the second top concave surface and the top of the second semiconductor mesa, and the sixth distance is greater than the fifth distance.

18 . The semiconductor structure of claim 16 , wherein:

the first undoped semiconductor layer wraps a bottom portion of the first doped semiconductor layer; and

the second undoped semiconductor layer wraps a bottom portion of the second doped semiconductor layer.

19 . The semiconductor structure of claim 16 , wherein:

the first ratio of the third distance to the first distance is 1 to 4; and

the second ratio of the fourth distance to the second distance is 0.5 to 0.9.

20 . The semiconductor structure of claim 19 , wherein the first distance is the same as the second distance.