Integrated circuit with a gate structure and method making the same

1 . A device comprising:

a first gate stack disposed on a substrate, the first gate stack including a first gate dielectric layer and a first gate electrode;

a first spacer layer disposed on the first gate stack and interfacing with the first gate dielectric layer and a portion of the substrate, the portion of the substrate being adjacent the first gate dielectric layer and free of any source/drain feature;

a second spacer layer disposed on the first spacer layer and formed of a different material than the first spacer layer; and

a first dielectric layer disposed between the first spacer layer and the first gate dielectric layer such that the first dielectric layer interfaces with the first gate dielectric layer and the first spacer layer, wherein a first portion of the first gate dielectric layer extends under the first dielectric layer such that the first portion of the first gate dielectric layer is disposed between the substrate and the first dielectric layer, the first portion of the first gate dielectric layer having a first thickness, and wherein a second portion of the first gate dielectric layer extends under the first gate electrode, the second portion of the first gate dielectric layer having a second thickness that is less than the first thickness.

2 . The device of claim 1 , wherein the first spacer layer has first sidewall surface facing the second spacer layer and an opposing second sidewall surface facing the first gate stack, and

wherein the first dielectric layer extends from the second sidewall of the first spacer layer to the first gate dielectric layer.

3 . The device of claim 1 , further comprising:

a second gate stack disposed on the substrate, the second gate stack including a second gate dielectric layer and a second gate electrode, the second gate dielectric layer being thicker than the first gate dielectric layer;

a third spacer layer disposed on the second gate stack and interfacing with the second gate dielectric layer;

a fourth spacer layer disposed on the third spacer layer and formed of a different material than the third spacer layer; and

a second dielectric layer disposed between the third spacer layer and the second gate dielectric layer such that the second dielectric layer interfaces with the second gate dielectric layer and the third spacer layer.

4 . The device of claim 3 , wherein the second gate dielectric layer is formed of a first material layer and a second material layer disposed on the first material layer, the second material layer having a u-shaped cross-sectional profile.

5 . The device of claim 4 , wherein the first material layer is wider than the second material layer.

6 . The device of claim 4 , wherein the first material layer interfaces with a bottom surface of the second dielectric layer, the bottom surface of the second dielectric layer facing the substrate.

7 . The device of claim 1 , further comprising a source/drain feature disposed on the substrate, and

wherein the first spacer layer and the second spacer layer interface with the source/drain feature.

8 . The device of claim 1 , wherein the first gate dielectric layer and the first gate electrode extend to a first height above the substrate, and

wherein the first spacer layer is disposed along an entire length of a first sidewall of the first gate stack such that the first spacer layer does not extend beyond the first height above the substrate, wherein no portion of the first spacer layer is disposed over a top surface of the first gate electrode, the top surface of the first gate electrode facing away from the substrate.

9 . A device comprising:

a first gate stack and a second gate stack disposed on a substrate;

a first dielectric material layer disposed on a sidewall of the first gate stack with a first thickness, wherein the first dielectric material layer is formed of the same material throughout the first dielectric material layer; and

a second dielectric material layer disposed on a sidewall of the second gate stack with a second thickness that is different than the first thickness, wherein the second dielectric material layer is formed of the same material throughout the second dielectric material layer, and

wherein the first gate stack includes a first gate dielectric layer and a first gate electrode over the first gate dielectric layer, wherein a first portion of the first gate dielectric layer extends under the first dielectric material layer such that the first portion of the first gate dielectric layer is disposed between the substrate and the first dielectric material layer, wherein a second portion of the first gate dielectric layer is disposed between and interfaces with a sidewall of the first gate electrode and a sidewall of the first dielectric material layer, wherein the first dielectric material layer physically contacts the first gate dielectric layer, and

wherein the second gate stack includes a second gate dielectric layer and a second electrode over the second gate dielectric layer, the second gate dielectric layer having a different thickness than that of the first gate dielectric layer, wherein a first portion of the second gate dielectric layer extends under the second dielectric material layer such that the first portion of the second gate dielectric layer is disposed between the substrate and the second dielectric material layer, wherein a second portion of the second gate dielectric layer is disposed between and interfaces with a sidewall of the second gate electrode and a sidewall of the second dielectric material layer, wherein the second dielectric material layer physically contacts the second gate dielectric layer.

10 . The device of claim 9 , further comprising a first spacer disposed along the first dielectric material layer and the first gate dielectric layer such that the first spacer interfaces with the first dielectric material layer and a sidewall of the first portion of the first gate dielectric layer,

wherein the first dielectric material layer is disposed between the second portion of the first gate dielectric layer and the first spacer.

11 . The device of claim 10 , further comprising a second spacer disposed on the first spacer, and

wherein the first spacer has a vertical portion extending vertically along the first dielectric material layer and a horizontal portion extending horizontally away from the first gate stack, and

wherein the second spacer interfaces with both the vertical portion and the horizontal portion of the first spacer.

12 . The device of claim 9 , wherein the second gate dielectric layer is formed of a first material layer and a second material layer, the second material layer being formed of a different material than the first material layer.

13 . The device of claim 12 , wherein the second material layer has a u-shaped profile and the first material layer extends horizontally beyond the u-shaped profile of the second material layer.

14 . The device of claim 9 , wherein the first gate dielectric layer is formed of the same material throughout the first gate dielectric layer.

15 . The device of claim 9 , wherein a top surface of the first gate stack is substantially coplanar with a top surface of the second gate stack, the top surfaces of the first and second gate stacks facing away from the substrate.

16 . A device comprising:

a first gate stack disposed over a substrate, the first gate stack extending to a first height above the substrate;

a first gate spacer disposed along an entire length of a first sidewall of the first gate stack such that the first gate spacer does not extend beyond the first height above the substrate, wherein a bottom surface of the first gate spacer interfaces the substrate;

a first dielectric material layer disposed along a first portion of the first sidewall of the first gate stack without being disposed along a second portion of the first sidewall, wherein the first dielectric material layer physically contacts the first gate spacer and the first portion of the first sidewall of the first gate stack;

a second gate stack disposed over a substrate;

a second gate spacer disposed along an entire length of a second sidewall of the second gate stack; and

a second dielectric material layer disposed along a first portion of the second sidewall of the second gate stack without being disposed along a second portion of the second sidewall,

wherein the second dielectric material layer physically contacts the second gate spacer and the first portion of the second sidewall of the second gate stack,

wherein the first gate stack includes a first gate dielectric layer and a first gate electrode over the first gate dielectric layer,

wherein the second gate stack includes a second gate dielectric layer and a second gate electrode over the second gate dielectric layer,

wherein the second gate dielectric layer does not extend between a bottom surface of the second spacer and the substrate,

wherein a portion of the first gate dielectric layer is sandwiched between a sidewall portion of the first dielectric material layer and a sidewall of the first gate electrode,

wherein a portion of the second gate dielectric layer is sandwiched between a sidewall portion of the second dielectric material layer and a sidewall of the second gate electrode.

17 . The device of claim 16 , wherein the second portion of the first sidewall is closer to the substrate than the first portion of the first sidewall of the first gate stack.

18 . The device of claim 16 , wherein the first gate spacer has a first L-shaped sidewall surface.

19 . The device of claim 16 , wherein the first dielectric material layer has a constant first thickness extending along the first portion of the first sidewall of the first gate stack,

wherein the first dielectric material layer is formed of the same material throughout the first dielectric material layer,

wherein the second dielectric material layer has a constant second thickness extending along the first portion of the second sidewall of the second gate stack,

wherein the second dielectric material layer is formed of the same material throughout the second dielectric material layer,

wherein the constant second thickness of the second dielectric material layer is thicker than the constant first thickness of the first dielectric material layer, and

wherein the second gate dielectric layer is thicker than the first gate dielectric layer.

20 . The device of claim 16 ,

wherein a first portion of the first gate dielectric layer extends under the first dielectric material layer such that the first portion of the first gate dielectric layer is disposed between the substrate and the first dielectric material layer, the first portion of the first gate dielectric layer having a first thickness, and

wherein a second portion of the first gate dielectric layer extends under the first gate electrode layer, the second portion of the first gate dielectric layer having a second thickness that is less than the first thickness.