Fin field-effect transistor device and method

1 . A semiconductor device comprising:

a substrate;

a fin protruding above the substrate;

isolation regions on opposing sides of the fin;

a gate structure over the fin;

a first interlayer dielectric (ILD) layer over the fin, over the isolation regions, and around the gate structure;

an air gap in the first ILD layer adjacent to the fin, wherein the fin is separated from the air gap by the first ILD layer, wherein the air gap extends from an upper surface of the first ILD layer distal from the substrate to an upper surface of the isolation regions; and

a dielectric layer over the first ILD layer, wherein the dielectric layer seals the air gap to form an enclosed cavity.

2 . The semiconductor device of claim 1 , further comprising a dummy contact plug that extends from the upper surface of the first ILD layer into the enclosed cavity, wherein the dummy contact plug is electrically isolated.

3 . The semiconductor device of claim 2 , further comprising a liner layer around the dummy contact plug, wherein a sidewall of the liner layer facing away from the dummy contact plug is exposed to the enclosed cavity.

4 . The semiconductor device of claim 3 , wherein the liner layer contacts and extends along sidewalls and a bottom of the dummy contact plug, wherein the liner layer along the bottom of the dummy contact plug contacts and extends along the upper surface of the isolation regions.

5 . The semiconductor device of claim 4 , wherein the liner layer is spaced apart from the first ILD layer.

6 . The semiconductor device of claim 4 , further comprising a second ILD layer over the first ILD layer, wherein a first portion of the second ILD layer is between the first ILD layer and the dielectric layer, and a second portion of the second ILD layer is between the dielectric layer and the air gap, wherein a lower surface of the first portion of the second ILD layer contacts and extends along the first ILD layer, wherein a lower surface of the second portion of the second ILD layer is exposed to the air gap.

7 . The semiconductor device of claim 6 , wherein an upper surface of the dummy contact plug is level with an upper surface of the second ILD layer distal from the substrate.

8 . The semiconductor device of claim 7 , wherein the dielectric layer contacts and extends along the upper surface of the second ILD layer and the upper surface of the dummy contact plug.

9 . The semiconductor device of claim 2 , further comprising:

a source/drain region over the fin adjacent to the gate structure;

a source/drain contact plug over the source/drain region and electrically coupled to the source/drain region, wherein the source/drain contact plug extends into the first ILD layer; and

another air gap in the first ILD layer and encircling the source/drain contact plug, wherein the dielectric layer seals the another air gap to form another enclosed cavity.

10 . The semiconductor device of claim 9 , further comprising a liner layer around the source/drain contact plug, wherein the liner layer is spaced apart from the first ILD layer.

11 . A semiconductor device comprising:

a fin protruding above a substrate;

isolation regions over the substrate and on opposing sides of the fin;

a gate structure over the fin;

a source/drain region over the fin adjacent to the gate structure;

a first interlayer dielectric (ILD) layer over the fin, over the isolation regions, over the source/drain region, and around the gate structure;

a via extending through the first ILD layer and electrically coupled to the source/drain region;

a first air gap in the first ILD layer around the via, wherein the via is spaced apart from the first ILD layer by the first air gap;

a second air gap in the first ILD layer, wherein a longitudinal axis of the second air gap is parallel to a longitudinal axis of the fin, wherein an upper surface of the isolation regions is exposed to the second air gap; and

a dielectric layer over the first ILD layer, wherein the dielectric layer seals the first air gap and the second air gap to form a first enclosed cavity and a second enclosed cavity, respectively.

12 . The semiconductor device of claim 11 , further comprising a conductive liner material along sidewalls of the via and along a bottom surface of the via facing the source/drain region, wherein first sidewalls of the conductive liner material facing away from the via are exposed to the first air gap.

13 . The semiconductor device of claim 12 , further comprising a dummy via extending into the second enclosed cavity, wherein the conductive liner material extends along sidewalls of the dummy via and along a bottom surface of the dummy via facing the substrate, wherein second sidewalls of the conductive liner material facing away from the dummy via are exposed to the second air gap.

14 . The semiconductor device of claim 13 , further comprising a second ILD layer between the first ILD layer and the dielectric layer, wherein the via and the dummy via extend through the second ILD layer, wherein a first upper surface of the via and a second upper surface of the dummy via are level with an upper surface of the second ILD layer distal from the substrate.

15 . The semiconductor device of claim 14 , wherein the conductive liner material is spaced apart from the first ILD layer and the second ILD layer.

16 . A semiconductor device comprising:

a substrate;

a first fin and a second fin that protrude above the substrate;

a gate structure over the first fin and the second fin;

a first source/drain region over the first fin and adjacent to the gate structure;

a first interlayer dielectric (ILD) layer over the first fin, over the second fin, over the first source/drain region, and around the gate structure;

a first air gap in the first ILD layer between the first fin and the second fin, wherein the first air gap is separated from the first fin and the second fin by the first ILD layer;

a second ILD layer over the first ILD layer and over the first air gap;

a dummy via extending through the second ILD layer into the first air gap, wherein the dummy via is electrically isolated;

a via extending through the first ILD layer and the second ILD layer and electrically coupled to the first source/drain region; and

a second air gap in the first ILD layer, in the second ILD layer, and around the via, wherein the via is spaced apart from the first ILD layer and the second ILD layer by the second air gap.

17 . The semiconductor device of claim 16 , wherein an upper surface of the dummy via and an upper surface of the via are level with an upper surface of the second ILD layer distal from the substrate.

18 . The semiconductor device of claim 16 , further comprising a dielectric layer over the second ILD layer, wherein the dielectric layer seals the first air gap and the second air gap to form a first enclosed cavity and a second enclosed cavity, respectively.

19 . The semiconductor device of claim 16 , wherein the first air gap extends closer to the substrate than the second air gap.

20 . The semiconductor device of claim 16 , further comprising an isolation region over the substrate and between the first fin and the second fin, wherein the first ILD layer is disposed over the isolation region, wherein the first air gap exposes an upper surface of the isolation region distal from the substrate.