Method of thinning a semiconductor substrate to high evenness and semiconductor substrate having a device layer of high evenness
A method of manufacturing a semiconductor device is described. The method includes providing a semiconductor substrate. The semiconductor substrate includes a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing includes dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.
1 . A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer;
removing the high-doped semiconductor substrate layer, wherein the removing comprises dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer; and
thinning the low-doped semiconductor etch stop layer to generate an exposed surface of the high-doped semiconductor device layer.
2 . The method of claim 1 , wherein thinning the low-doped semiconductor etch stop layer comprises chemical mechanical polishing (CMP) or chemical etching.
3 . The method of claim 1 , wherein removing the high-doped semiconductor substrate layer comprises:
partially removing the high-doped semiconductor substrate layer by grinding;
followed by completely removing the residual high-doped semiconductor substrate layer by the dopant selective chemical etching.
4 . The method of claim 1 , wherein a total thickness variation (TTV) of the low-doped semiconductor etch stop layer after removing the high-doped semiconductor substrate layer is equal to or less than 1.0 μm.
5 . The method of claim 1 , wherein the low-doped semiconductor etch stop layer is an epitaxial layer.
6 . The method of claim 1 , wherein the low-doped semiconductor etch stop layer is doped by a first dopant and counter-doped by a second dopant of opposite dopant polarity than the first dopant.
7 . The method of claim 1 , wherein a total thickness variation (TTV) of the high-doped semiconductor device layer after thinning the low-doped semiconductor etch stop layer is equal to or less than 1.0 μm.
8 . The method of claim 1 , wherein the high-doped semiconductor device layer is arranged on a low-doped semiconductor device layer, and wherein the low-doped semiconductor device layer and the high-doped semiconductor device layer have a total thickness of equal to or less than 15 μm, or 10 μm, or 5 μm, or 3 μm, or 2 μm.
9 . The method of claim 1 , further comprising:
patterning the low-doped semiconductor etch stop layer to generate alignment features which are configured to appear as visible alignment marks in or on the exposed surface of the high-doped semiconductor device layer after thinning.
10 . The method of claim 1 , wherein the semiconductor substrate further comprises a low-doped semiconductor device layer arranged between the high-doped semiconductor device layer and a functional layer stack.
11 . The method of claim 1 , wherein the semiconductor substrate further comprises a functional layer stack arranged on the high-doped semiconductor device layer.
12 . The method of claim 11 , wherein the functional layer stack includes a wafer bonding layer having a thickness between 50 nm and 200 nm.