IP Library Granted Patent US 12701816
Granted Patent B2
US 12701816 · App. 18/356,879 · Granted Aug 4, 2026

Method for producing a solar cell

Inventors: Marc Hofmann (Freiburg, DE); Sebastian Mack (Freiburg, DE); Bishal Kafle (Freiburg, DE); Jochen Rentsch (Freiburg, DE); Nabeel Wahab Khan (Freiburg, DE); Laurent Clochard (Dublin, IE); Edward Duffy (Dublin, IE)
Assignees: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.; Ultra High Vacuum Solutions Ltd
H10F71/121H10F10/165
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Quick Facts
Patent No.
US 12701816
App. No.
18/356,879
Granted
Aug 4, 2026
Kind
B2
Abstract

The embodiments relate to a method for producing a solar cell having a rear-side contact with a tunnel barrier. A monocrystalline wafer having a front side and a rear side may be provided with silicon and a dopant. A tunnel barrier is produced on the wafer, and a polycrystalline or amorphous layer is deposited on the tunnel barrier. The polycrystalline or amorphous layer includes silicon and a dopant. The polycrystalline or amorphous layer is removed on the front side by gas-phase etching.

Claims (23)

1 . A method for producing a solar cell having a rear-side contact with a tunnel barrier, the method comprises:

providing a monocrystalline wafer having a front side and a rear side, the wafer comprising silicon and a dopant;

producing a first tunnel barrier on the front side of the wafer and producing a second tunnel barrier on the rear side of the wafer;

depositing a polycrystalline or amorphous layer on the first and second tunnel barriers, wherein the polycrystalline or amorphous layer comprises silicon; and

removing the polycrystalline or amorphous layer on the front side by gas-phase etching, wherein an etchant for the gas-phase etching comprises F 2 ,

wherein for the gas-phase etching, the wafer rests on a conveyor belt and

wherein the gas-phase etching is stopped upon reaching the first tunnel barrier at the front side.

2 . The method according to claim 1 , wherein for the gas-phase etching, the wafer is heated to a temperature from about 120° C. to about 260° C.

3 . The method according to claim 2 , wherein for gas-phase etching, the wafer is heated to a temperature from about 190° C. to about 200° C.

4 . The method according to claim 1 , wherein the gas-phase etching is carried out with a gas phase, and the F 2 concentration is about 20% to about 30%.

5 . The method according to claim 4 , wherein the gas-phase etching is carried out with a gas phase which is supplied with F 2 at a flow rate from about 5 slm to about 7 slm.

6 . The method according to claim 1 wherein the gas-phase etching is carried out with a gas phase which is supplied with N 2 at a flow rate from about 0.75 slm to about 1.25 slm.

7 . The method according to claim 6 , wherein the gas-phase etching is carried out between about 15 sec. and about 35 sec.

8 . The method according to claim 1 , wherein the gas-phase etching is carried out in a gas phase which has a pressure from about 960 mbar to about 1040 mbar.

9 . The method according to claim 1 , wherein the gas-phase etching is continued when reaching the tunnel barrier at the front side so that a surface patterning is produced on the front side of the wafer.

10 . The method according to claim 1 , further comprising:

diffusing boron into the wafer; and

removing the boron-containing layer on the rear side.

11 . The method according to claim 10 , wherein the borosilicate glass layer forming when boron is diffused on the rear side and/or on the front side of the wafer is removed in a wet chemical process.

12 . The method according to claim 10 , wherein the tunnel barrier has a thickness from about 1 nm to about 5 nm.

13 . The method according to claim 12 , wherein the polycrystalline or amorphous layer has a thickness from about 30 nm to about 300 nm.

14 . The method according to claim 13 , wherein the tunnel barrier comprises SiO x wherein 1≤x≤2.

15 . The method according to claim 1 , wherein the polycrystalline or amorphous layer further contains at least one dopant.