Micro-LED and method of manufacture
A method of manufacturing a micro-LED comprises the steps of forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material, and forming an electrically-insulating mask layer on the n-doped connecting layer. The method comprises the steps of removing a portion of the mask to expose an exposed region of the n-doped connecting layer, and forming an LED structure on the exposed region of the n-doped connecting layer. A method of manufacturing an array of micro-LEDs comprises the step of removing a portion of the mask to expose an array of exposed regions of the n-doped connecting layer, and forming an LED structure on each exposed region of the n-doped connecting layer. A micro-LED and array of micro-LEDs are also provided.
1 . A method of manufacturing a micro-LED, comprising the steps of:
forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material;
forming an electrically-insulating mask layer on the n-doped connecting layer;
removing only a portion of the electrically-insulating mask layer to expose an exposed region of the n-doped connecting layer, such that the exposed region is an opening in the electrically-insulating mask layer; and
forming an LED structure on the exposed region of the n-doped connecting layer.
2 . A method according to claim 1 , comprising the first step of electrochemically porosifying a region of III-nitride material, to form the porous region of III-nitride material.
3 . A method according to claim 1 , comprising the step of forming the porous region of III-nitride material by electrochemical porosification through a non-porous layer of III-nitride material, such that the non-porous layer of III-nitride material forms a non-porous intermediate layer between the porous region and the n-doped III-nitride connecting layer, optionally in which the non-porous intermediate layer has a thickness of between 1 nm and 3000 nm.
4 . A method according to claim 1 , in which the n-doped connecting layer of III-nitride material is formed over a stack of multiple porous layers of III-nitride material, optionally in which the stack of porous layers comprises a porous Distributed Bragg Reflector (DBR), such that the method comprises the step of forming an n-doped connecting layer of III-nitride material over a porous DBR of III-nitride material.
5 . A method according to claim 4 , in which the stack of porous layers is a stack of alternating porous and non-porous layers, optionally in which the porous layers have a thickness of between 10 nm and 200 nm, and the non-porous layers have a thickness of between 5 nm and 180 nm.
6 . A method according to claim 1 , in which the porous region or each porous layer has a porosity of between 10% and 90% porous, and/or in which the n-doped connecting layer of III-nitride material has a thickness of between 200 nm and 2000 nm and a charge carrier concentration of >1×10 18 cm −3 .
7 . A method according to claim 1 , in which the mask layer is formed from one of: SiO 2 , SIN, SiON, AlO x .
8 . A method according to claim 1 , in which the mask layer has a thickness of between 5 nm and 1000 nm.
9 . A method according to claim 1 , in which the exposed regions of the connecting layer are circular, square, rectangular, hexagonal, or triangular in shape.
10 . A method according to claim 1 , comprising the step of, after the n-doped portion, the light emitting region and the p-doped portion have been formed, removing a second portion of the mask to expose a second exposed region of the n-doped connecting layer; and
forming an electrical contact in the second exposed region of the n-doped connecting layer.
11 . A method according to claim 1 , in which the exposed region has a width and length of between 0.05 μm and 100 μm.
12 . A method according to claim 1 , in which the step of forming the LED structure comprises forming, on the exposed region of the n-doped connecting layer:
an n-doped portion;
a p-doped portion; and
a light emitting region located between the n-doped portion and a p-doped portion;
in which the light-emitting region comprises one or more III-nitride light-emitting layers, and in which the or each light-emitting layer comprises a nanostructured layer comprising fragmented or discontinuous quantum wells.
13 . A method of manufacturing an array of micro-LEDs, comprising:
forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material;
forming an electrically-insulating mask layer on the n-doped III-nitride layer;
removing only a portion of the electrically-insulating mask layer to expose an array of exposed regions of the n-doped connecting layer, such that the exposed regions are openings in the electrically-insulating mask layer; and
forming an LED structure on each exposed region of the n-doped connecting layer.
14 . A micro-LED, comprising:
an n-doped connecting layer of III-nitride material over a porous region of III-nitride material;
an electrically-insulating mask layer on the n-doped connecting layer of III-nitride material; and
an LED structure,
in which at least a portion of the LED structure extends through a gap in the electrically-insulating mask layer, and is in contact with the n-doped connecting layer of III-nitride material.
15 . A micro-LED according to claim 14 , in which the LED structure comprises:
an n-doped portion;
a p-doped portion; and
a light emitting region located between the n-doped portion and a p-doped portion, optionally in which the n-doped portion comprises an n-doped III-nitride layer.
16 . A micro-LED according to claim 15 , in which the light-emitting region comprises one or more III-nitride light-emitting layers, and in which the or each light-emitting layer comprises a quantum well.
17 . A micro-LED according to claim 16 , in which the or each light-emitting layer comprises a III-nitride material with an atomic indium content of between 10-40%, or between 12-18%, or between 20-30%, or between 30-40%, and/or in which the one or more light-emitting layers have the composition In x Ga 1-x N, in which 0.10≤x≤0.40.
18 . A micro-LED according to claim 15 , in which the light-emitting region comprises one or more InGaN quantum wells, and/or in which the LED comprises a cap layer of III-nitride material between the quantum wells and the p-doped portion.
19 . A micro-LED according to claim 15 , in which the p-doped portion comprises a p-doped III-nitride layer and a p-doped aluminium gallium nitride layer positioned between the p-doped III-nitride layer and the light emitting region, optionally in which the p-doped aluminium nitride layer is an electron-blocking-layer (EBL) between the cap layer and the p-type layer, in which the electron-blocking-layer contains 5-25 at % aluminium.
20 . An array of micro-LEDs, comprising a plurality of micro-LEDs according to claim 15 , formed on a substrate.
21 . A micro-LED according to claim 15 , in which the light-emitting region comprises one or more III-nitride light-emitting layers, and in which the or each light-emitting layer comprises a nanostructured layer comprising fragmented or discontinuous quantum wells.
22 . A micro-LED according to claim 14 , comprising a non-porous intermediate layer of III-nitride material positioned between the porous region and the connecting layer.
23 . An array of micro-LEDs, comprising:
an n-doped connecting layer of III-nitride material over a porous region of III-nitride material;
an electrically-insulating mask layer on the n-doped connecting layer of III-nitride material;
a plurality of gaps in the electrically-insulating mask layer, and
a plurality of LED structures,
in which at least a portion of each LED structure extends through a gap in the electrically-insulating mask layer, and is in contact with the n-doped connecting layer of III-nitride material.