Semiconductor structures with adjustable light-emitting wavelengths and manufacturing methods thereof
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a silicon substrate having several through-silicon-vias therein; a first semiconductor layer located in each through-silicon-via and on the silicon substrate, an active layer located on the first semiconductor layer, and a second semiconductor layer located on the active layer, where a conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer, a material of the first semiconductor layer a group III nitride, a material of the active layer a group III nitride, and a material of the second semiconductor layer include a group III nitride.
1 . A semiconductor structure, comprising:
a silicon substrate provided with one or more through-silicon-vias in the silicon substrate;
a first semiconductor layer located in each of the one or more through-silicon-vias and on the silicon substrate;
an active layer located on the first semiconductor layer, wherein the active layer is located on a top surface of the first semiconductor layer; and
a second semiconductor layer located on the active layer,
wherein a conductivity type of the second semiconductor layer is opposite to a conductivity type of the first semiconductor layer, a material of the first semiconductor layer comprises a group III nitride, a material of the active layer comprises a group III nitride, and a material of the second semiconductor layer comprises a group III nitride;
wherein the active layer includes an indium element; and
wherein a composition ratio of the indium element in the active layer increases as a size of the top surface of the first semiconductor layer decreases and the composition ratio of the indium element in the active layer decreases as the size of the top surface of the first semiconductor layer increases.
2 . The semiconductor structure of claim 1 , wherein a dielectric layer is disposed between the first semiconductor layer and an upper surface of the silicon substrate.
3 . The semiconductor structure of claim 2 , wherein the active layer is located on a top surface and a side surface of the first semiconductor layer.
4 . The semiconductor structure of claim 3 , wherein
an angle between the side surface and the top surface ranges from 40° to 70°;
the composition ratio of the indium element in the active layer located on the top surface is greater than the composition ratio of the indium element in the active layer located on the side surface.
5 . The semiconductor structure of claim 2 , wherein a cross section of the first semiconductor layer along a thickness direction is triangular, and the active layer is located on a side surface of the first semiconductor layer.
6 . The semiconductor structure of claim 1 , wherein a depth-to-width ratio of each of the one or more through-silicon-vias is greater than 1:1.
7 . The semiconductor structure of claim 1 , wherein there is a plurality of through-silicon-vias, a common electrode is disposed on a side of the silicon substrate away from the second semiconductor layer, and the common electrode is electrically coupled with the first semiconductor layer in each of the through-silicon-vias.
8 . The semiconductor structure of claim 1 , further comprising:
a group III nitride epitaxial layer located on a first substrate,
a bonding layer bonding the group III nitride epitaxial layer and the silicon substrate together, and
one or more first through-holes provided in the bonding layer, each of the one or more first through-holes communicating with a corresponding through-silicon-via, the first semiconductor layer being located in the one or more first through-holes to connect with the group III nitride epitaxial layer.
9 . The semiconductor structure of claim 8 , wherein there are a plurality of through-silicon-vias and a plurality of first through-holes respectively, a common electrode is provided on one or both of a sidewall of the silicon substrate or a sidewall of the group III nitride epitaxial layer, and the common electrode is electrically coupled with the first semiconductor layer in each of the through-silicon-vias.
10 . A method of manufacturing a semiconductor structure, comprising:
providing a silicon substrate, providing a group III nitride epitaxial layer located on a first substrate; and providing a bonding layer between the group III nitride epitaxial layer and the silicon substrate, the group III nitride epitaxial layer and the silicon substrate being bonded together through the bonding layer;
patterning the silicon substrate and the bonding layer to respectively form one or more through-silicon-vias and one or more first through-holes each corresponding to one of the one or more through-silicon-vias, each of the one or more first through-holes exposing the group III nitride epitaxial layer, each of the one or more through-silicon-vias communicating with a corresponding first through-hole;
epitaxially growing the group III nitride epitaxial layer to form a first semiconductor layer in each of the one or more first through-holes and each of the one or more through-silicon-vias and on the patterned silicon substrate; and
epitaxially growing an active layer and a second semiconductor layer on the first semiconductor layer in sequence, a conductivity type of the second semiconductor layer being opposite to a conductivity type of the first semiconductor layer, a material of the first semiconductor layer comprising a group III nitride, a material of the active layer comprising a group III nitride, and a material of the second semiconductor layer comprising a group III nitride.
11 . The method of manufacturing the semiconductor structure of claim 10 , wherein the active layer is formed on a top surface of the first semiconductor layer by etching or using a mask layer.
12 . The method of manufacturing the semiconductor structure of claim 11 , wherein the active layer comprises an indium element; the smaller a size of the top surface of the first semiconductor layer is, the greater a composition ratio of the indium element in the active layer is; and the larger the size of the top surface of the first semiconductor layer is, the less the composition ratio of the indium element in the active layer is.
13 . The method of manufacturing the semiconductor structure of claim 10 , further comprising: before epitaxially growing the first semiconductor layer, forming a patterned dielectric layer on the patterned silicon substrate.
14 . The method of manufacturing the semiconductor structure of claim 10 , further comprising:
before patterning the silicon substrate to form the one or more through-silicon-vias, forming a dielectric layer on a side of the silicon substrate away from the group III nitride epitaxial layer;
patterning the dielectric layer and the silicon substrate in a same process; or
patterning the dielectric layer, and etching the silicon substrate by using the patterned dielectric layer as a mask.
15 . The method of manufacturing the semiconductor structure of claim 13 , further comprising: forming the active layer on a top surface and a side surface of the first semiconductor layer.
16 . The method of manufacturing the semiconductor structure of claim 15 , wherein the active layer comprises an indium element; the larger an angle between the side surface and the top surface is, the less a composition ratio of the indium element in the active layer on the side surface is; and the smaller the angle between the side surface and the top surface is, the greater the composition ratio of the indium element in the active layer on the side surface is.
17 . The method of manufacturing the semiconductor structure of claim 15 , wherein a cross section of the first semiconductor layer along a thickness direction is triangular, and the method further comprising: forming the active layer on the side surface of the first semiconductor layer.
18 . The method of manufacturing the semiconductor structure of claim 10 , further comprising: etching the bonding layer to peel off the group III nitride epitaxial layer from the silicon substrate.