IP Library Granted Patent US 12,701,861
Granted Patent B2
US 12,701,861 · App. 18/260,976 · Granted Aug 4, 2026

Display device including a structure in which three layers having electrical circuits are stacked

Inventors: Shunpei Yamazaki (Tokyo, JP); Takayuki Ikeda (Atsugi, JP); Tatsuya Onuki (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10K59/1213H10K59/873H10K59/879
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Quick Facts
Patent No.
US 12,701,861
App. No.
18/260,976
Granted
Aug 4, 2026
Kind
B2
Abstract

A novel display device is provided. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and a functional circuit. The second layer includes a pixel circuit. The third layer includes a display element. The pixel circuit has a function of controlling light emission of the display element. The driver circuit has a function of controlling the pixel circuit. The functional circuit has a function of controlling the driver circuit. The first layer includes a first transistor with a semiconductor layer containing silicon in a channel formation region. The second layer includes a second transistor with a semiconductor layer containing a metal oxide in a channel formation region.

Claims (21)

1 . A display device comprising:

a first layer including a first gate driver circuit, a second gate driver circuit, a first source driver circuit, a second source driver circuit, and a functional circuit;

a second layer including a first pixel circuit in a first region and a second pixel circuit in a second region; and

a third layer including a first display element and a second display element,

wherein the first pixel circuit is electrically connected to the first gate driver circuit, the first source driver circuit, and the first display element,

wherein the second pixel circuit is electrically connected to the second gate driver circuit, the second source driver circuit, and the second display element,

wherein the first region of the second layer has a region overlapping with the first gate driver circuit and the first source driver circuit,

wherein the second region of the second layer overlaps with the second gate driver circuit and the second source driver circuit, and

wherein the functional circuit is configured to control the first gate driver circuit, the second gate driver circuit, the first source driver circuit, and the second source driver circuit.

2 . The display device according to claim 1 ,

wherein the first layer comprises a first transistor containing silicon in a channel formation region,

wherein the second layer comprises a second transistor containing a metal oxide in a channel formation region.

3 . The display device according to claim 2 ,

wherein the metal oxide comprises In, an element M, and Zn, and,

wherein the element M is Al, Ga, Y, or Sn.

4 . The display device according to claim 1 ,

wherein each of the first display element and the second display element comprises an organic EL element, and

wherein the organic EL element is a display element processed by a photolithography method.

5 . The display device according to claim 1 ,

wherein the second layer is positioned over the first layer, and

wherein the third layer is positioned over the second layer.