IP Library › Granted Patent US 12701872
Granted Patent B2
US 12701872 · App. 17/433,041 · Granted Aug 4, 2026

Array substrate having an isolation pillar in a hole border area, preparation method thereof and display device

Inventors: Weiyun Huang (Beijing, CN); Yao Huang (Beijing, CN); Chao Zeng (Beijing, CN); Yue Long (Beijing, CN); Tianyi Cheng (Beijing, CN)
Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
H10K59/124H10K59/122H10K59/1201H10K59/8731
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Quick Facts
Patent No.
US 12701872
App. No.
17/433,041
Granted
Aug 4, 2026
Kind
B2
Abstract

The present disclosure provides an array substrate, a preparation method thereof, and a display device. The array substrate has an opening area and a hole border area. A method of preparation of the array substrate includes: forming a source-drain metal layer on a side of the base substrate, wherein the source-drain metal layer is formed with a first isolation pillar surrounding the opening area in the hole border area, and the first isolation pillar includes a first metal layer and a second metal layer located on a side of the first metal layer away from the base substrate; forming a planarization layer covering at least a lateral surface of each first metal layer; forming a pixel electrode layer; forming a protective layer covering the pixel electrode layer, the protective layer exposing the hole border area; removing a part of the planarization layer located in the hole border area; partially etching the first metal layer from the lateral surface to form a third metal layer; removing the protective layer; forming an organic light emitting layer and a common electrode layer in sequence. The preparation method of the array substrate can improve the yield of the array substrate.

Claims (25)

1 . An array substrate, comprising:

an opening, a hole border area surrounding the opening, and a base substrate formed with the opening;

a drive circuit layer provided on a side of the base substrate, wherein the drive circuit layer comprises a source-drain metal layer formed with a second isolation pillar surrounding the opening in the hole border area, the second isolation pillar comprises a third metal layer and a second metal layer located on a side of the third metal layer away from the base substrate, and the second isolation pillar is formed with a partition groove located on a side of the second metal layer close to the base substrate, so that an orthographic projection of the third metal layer on the second metal layer is within a range of the second metal layer;

a support portion provided on the side of the second metal layer close to the base substrate and filling part of the partition groove;

a pixel electrode layer provided on a side of the drive circuit layer away from the base substrate;

an organic light emitting layer provided on a side of the pixel electrode layer away from the base substrate, and divided into a plurality of disconnected parts in the hole border area by the second isolation pillar; and

a common electrode layer provided on a side of the organic light emitting layer away from the base substrate, and divided into a plurality of disconnected parts in the hole border area by the second isolation pillar, wherein:

the second isolation pillar further comprises a fourth metal layer, the fourth metal layer is provided on a surface of the third metal layer close to the base substrate, an orthographic projection of the third metal layer on the fourth metal layer is located within a range of the fourth metal layer, and an orthographic projection of the second metal layer on the fourth metal layer is located inside the range of the fourth metal layer; and

the support portion supports the second metal layer, the support portion is located at least at a corner of a junction of the third metal layer and the second metal layer, and the support portion is a photoresist material that is not exposed to light and remains in the partition groove.

2 . The array substrate of claim 1 , wherein the support portion further covers a lateral surface of the third metal layer.

3 . The array substrate according to claim 2 , wherein the array substrate is implemented in a display device.

4 . The array substrate according to claim 1 , wherein the support portion is also located at a corner of a junction of the third metal layer and the fourth metal layer.

5 . The array substrate according to claim 4 , wherein the array substrate is implemented in a display device.

6 . The array substrate according to claim 1 , wherein the array substrate is implemented in a display device.

7 . An array substrate, comprising:

an opening, a hole border area surrounding the opening, and a base substrate formed with the opening;

a drive circuit layer provided on a side of the base substrate, wherein the drive circuit layer comprises a source-drain metal layer formed with a second isolation pillar surrounding the opening in the hole border area, the second isolation pillar comprises a third metal layer and a second metal layer located on a side of the third metal layer away from the base substrate, and the second isolation pillar is formed with a partition groove located on a side of the second metal layer close to the base substrate, so that an orthographic projection of the third metal layer on the second metal layer is within a range of the second metal layer;

a support portion provided on the side of the second metal layer close to the base substrate and filling part of the partition groove;

a pixel electrode layer provided on a side of the drive circuit layer away from the base substrate;

an organic light emitting layer provided on a side of the pixel electrode layer away from the base substrate, and divided into a plurality of disconnected parts in the hole border area by the second isolation pillar; and

a common electrode layer provided on a side of the organic light emitting layer away from the base substrate, and divided into a plurality of disconnected parts in the hole border area by the second isolation pillar, wherein:

the support portion supports the second metal layer, and the support portion is a photoresist material that is not exposed to light and remains in the partition groove.

8 . The array substrate according to claim 7 , wherein the support portion is located at least at a corner of a junction of the third metal layer and the second metal layer.

9 . The array substrate of claim 8 , wherein the support portion further covers a lateral surface of the third metal layer.

10 . The array substrate according to claim 8 , wherein the second isolation pillar further comprises a fourth metal layer provided on a surface of the third metal layer close to the base substrate, and the support portion is also located at a corner of a junction of the third metal layer and the fourth metal layer.