Thin film transistor array substrate with overlapping light shielding layers
A thin film transistor array substrate can include a substrate having a plurality of subpixel areas in which a gate line, a data line and a power line are formed to cross one another, a first shielding layer provided on the substrate in any one of the plurality of subpixel areas, a first buffer layer provided on the first shielding layer, a second shielding layer provided on the first buffer layer to overlap the first shielding layer, a second buffer layer provided on the second shielding layer, and a thin film transistor provided in an area overlapped with the first shielding layer and the second shielding layer on the second buffer layer.
1 . A thin film transistor array substrate comprising:
a substrate having a plurality of subpixel areas in which a gate line, a data line and a power line cross one another;
a first shielding layer provided on the substrate in any one of the plurality of subpixel areas;
a first buffer layer provided on the first shielding layer;
a second shielding layer provided on the first buffer layer to overlap the first shielding layer;
a second buffer layer provided on the second shielding layer; and
a thin film transistor provided in an area overlapped with the first shielding layer and the second shielding layer on the second buffer layer,
wherein the power line is disposed on a same layer as the first shielding layer,
wherein the first buffer layer is not disposed between the power line and the second shielding layer,
wherein the power line is provided in a same layer as the first shielding layer, and
wherein the second shielding layer directly contacts and covers an upper and both side surfaces of the power line.
2 . The thin film transistor array substrate of claim 1 , wherein the first shielding layer and the second shielding layer are made of a conductive material capable of shielding light.
3 . The thin film transistor array substrate of claim 1 , wherein an area of the second shielding layer is larger than an area of the first shielding layer.
4 . The thin film transistor array substrate of claim 1 , wherein the first buffer layer covers an end of the first shielding layer adjacent to the gate line, the data line and the power line, and
the second shielding layer covers an end of the first buffer layer adjacent to the gate line, the data line and the power line.
5 . The thin film transistor array substrate of claim 1 , wherein the second buffer layer is provided on an upper surface of the second shielding layer, and
the second buffer layer is not provided on the gate line, the data line and the power line.
6 . The thin film transistor array substrate of claim 1 , wherein the thin film transistor includes:
a semiconductor layer provided on the second buffer layer;
a gate insulating layer provided on the semiconductor layer;
a gate electrode provided on the gate insulating layer;
a source electrode connected to one side of the semiconductor layer; and
a drain electrode connected to another side of the semiconductor layer.
7 . The thin film transistor array substrate of claim 6 , further comprising a first contact hole exposing the first shielding layer,
wherein the first shielding layer is electrically connected to the source electrode through the first contact hole.
8 . The thin film transistor array substrate of claim 7 , wherein the first contact hole passes through the first buffer layer, the second shielding layer, and the second buffer layer, and
inner sides of the first contact hole are composed of sides of the first buffer layer and sides of the second buffer layer.
9 . The thin film transistor array substrate of claim 6 , further comprising a second contact hole exposing the second shielding layer,
wherein the second shielding layer is electrically connected to the gate electrode through the second contact hole.
10 . The thin film transistor array substrate of claim 9 , wherein the second contact hole passes through the second buffer layer, and
inner sides of the second contact hole are composed of sides of the second buffer layer.
11 . A thin film transistor array substrate comprising:
a substrate having a plurality of subpixel areas in which a gate line, a data line and a power line are formed to cross one another;
a thin film transistor including a gate electrode, a source electrode and a drain electrode;
a first shielding layer provided on the substrate and electrically connected to the source electrode;
a first buffer layer provided on the first shielding layer; and
a second shielding layer provided on the first buffer layer and electrically connected to the gate electrode,
wherein the power line is provided in a same layer as the first shielding layer, and
wherein the second shielding layer directly contacts and covers an upper surface and both side surfaces of the power line.
12 . The thin film transistor array substrate of claim 11 , wherein the thin film transistor array substrate further comprises a second buffer layer provided on the second shielding layer, and
the thin film transistor is provided in an area overlapped with the first shielding layer and the second shielding layer on the second buffer layer.
13 . The thin film transistor array substrate of claim 12 , wherein the thin film transistor array substrate further comprises a first contact hole that passes through the first buffer layer, the second shielding layer, and the second buffer layer, and
the first shielding layer is electrically connected to the source electrode through the first contact hole.
14 . The thin film transistor array substrate of claim 12 , wherein the thin film transistor array substrate further comprises a second contact hole that passes through the second buffer layer, and
the second shielding layer is electrically connected to the gate electrode through the second contact hole.
15 . The thin film transistor array substrate of claim 11 ,
wherein the first buffer layer is not disposed between the power line and the second shielding layer.