Semiconductor device structure and manufacturing method thereof
A manufacturing method for a semiconductor device structure and the semiconductor device structure are disclosed. The method includes forming backside connection structures by sequentially forming heat transfer layers stacked upon one another and backside metallization structures sandwiched between the heat transfer layers. The formation of at least one heat transfer layer involves performing an annealing process to turn an insulating material layer into an insulating nanostructured material layer with nano grains and dopants distributed along grain boundaries of the nano grains.
1 . A manufacturing method of a semiconductor device structure, comprising:
forming a device layer on a first surface of a semiconductor substrate, wherein the device layer is formed with a plurality of transistors;
performing a thinning process to the semiconductor substrate, thinning the semiconductor substrate from a second surface of the semiconductor substrate opposite to the first surface;
forming a material layer containing dopants on the second surface of the thinned semiconductor substrate, wherein the material layer is formed with first nano grains of a first grain size;
forming a cap layer on the material layer covering the material layer;
performing an annealing process to the cap layer and the material layer to turn the material layer into a nanostructured material layer, wherein the nanostructured material layer is formed with second nano grains of a second grain size, and the second grain size is larger than the first grain size; and
forming metallization structures in the nanostructured material layer.
2 . The method as claimed in claim 1 , wherein forming a material layer containing dopants includes performing a deposition process and performing in-situ doping of the dopants.
3 . The method as claimed in claim 2 , wherein forming the material layer includes depositing a layer of an insulating material selected from diamond, crystalline aluminum nitride (AlN), crystalline silicon carbide (SiC), or crystalline boron nitride (BN).
4 . The method as claimed in claim 3 , wherein the dopants include at least one selected from boron (B), silicon (Si), aluminum (Al), titanium (Ti), zirconium (Zr), niobium (Nb), yttrium (Y), chromium (Cr), nickel (Ni), manganese (Mn), molybdenum (Mo), ruthenium (Ru), strontium (Sr), cobalt (Co), or iron (Fe).
5 . The method as claimed in claim 1 , wherein forming the material layer with dopants includes forming a diamond layer by performing a chemical vapor deposition process with in-situ doping.
6 . The method as claimed in claim 5 , wherein the dopants include at least one element selected from Al, Si, Nb, Mn, B, or combinations thereof.
7 . The method as claimed in claim 1 , wherein forming the material layer with dopants includes forming a crystalline AlN layer by performing a physical vapor deposition process and co-sputtering the dopants.
8 . The method as claimed in claim 7 , wherein the dopants include at least one element selected from Ti, Zr, Nb, Y, Cr, Ni, Si, Mn, Ru or combinations thereof.
9 . The method as claimed in claim 1 , wherein forming metallization structures in the nanostructured material layer includes forming metallic power rails in the nanostructured material layer.
10 . A manufacturing method of a semiconductor device structure, comprising:
providing a semiconductor substrate having through vias embedded therein;
forming a device layer on a first side of the semiconductor substrate, wherein the device layer is formed with a plurality of transistors;
forming a first material layer on a second side of the semiconductor substrate opposite to the first side and performing doping to the first material layer, wherein the first material layer is formed with first nano grains of a first grain size and contains first dopants;
forming a first cap layer on the first material layer covering the first material layer;
forming a first nanostructured material layer below the first cap layer by performing a first laser annealing process, wherein the first nanostructured material layer is formed with second nano grains of a second grain size that is larger than the first grain size, and the first dopants are distributed along grain boundaries of the second nano grains;
forming first metallization structures in the first nanostructured material layer;
forming a second material layer over the first material layer and performing doping to the second material layer, wherein the second material layer is formed with third nano grains of a third grain size and contains second dopants;
forming a second cap layer on the second material layer covering the second material layer;
forming a second nanostructured material layer below the second cap layer by performing a second laser annealing process, wherein the second material layer is formed with fourth nano grains of a fourth grain size that is larger than the third grain size, and the second dopants are distributed along grain boundaries of the fourth nano grains; and
forming second metallization structures in the second nanostructured material layer.
11 . The method as claimed in claim 10 , wherein forming first metallization structures in the first nanostructured material layer includes forming connection patterns in the first nanostructured material layer, and the connection patterns are connected with the through vias and are electrically connected with the plurality of transistors.
12 . The method as claimed in claim 11 , wherein forming second metallization structures in the second nanostructured material layer includes forming metallic power rails in the second nanostructured material layer, and the metallic power rails are electrically connected with the first metallization structures and the plurality of transistors.
13 . The method as claimed in claim 12 , wherein the fourth grain size is different to the second grain size, and the second nanostructured material layer has a thermal conductivity higher than that of the first nanostructured material layer.
14 . The method as claimed in claim 10 , wherein materials of the first nanostructured material layer and the second nanostructured material layer include insulating materials selected from diamond, crystalline aluminum nitride (AlN), crystalline silicon carbide (SiC), or crystalline boron nitride (BN).
15 . The method as claimed in claim 14 , wherein the first dopants and the second dopants include at least one selected from boron (B), silicon (Si), aluminum (Al), titanium (Ti), zirconium (Zr), niobium (Nb), yttrium (Y), chromium (Cr), nickel (Ni), manganese (Mn), molybdenum (Mo), ruthenium (Ru), strontium (Sr), cobalt (Co), or iron (Fe).
16 . A semiconductor device structure, comprising:
a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a device layer disposed on the first surface of the semiconductor substrate, wherein the device layer includes a plurality of transistors; and
backside connection structures, disposed on the second surface of the semiconductor substrate and electrically connected with the plurality of transistors,
wherein the backside connection structures include backside metallization structures and at least one insulating nanostructured material having nano grains and dopants distributed along grain boundaries of the nano grains.
17 . The structure as claimed in claim 16 , wherein the nano grains have an average grain size larger than 50 nm.
18 . The structure as claimed in claim 17 , wherein the insulating nanostructured material includes diamond, crystalline aluminum nitride (AlN), crystalline silicon carbide (SiC), or crystalline boron nitride (BN).
19 . The structure as claimed in claim 18 , wherein the dopants include at least one selected from boron (B), silicon (Si), aluminum (Al), titanium (Ti), zirconium (Zr), niobium (Nb), yttrium (Y), chromium (Cr), nickel (Ni), manganese (Mn), molybdenum (Mo), ruthenium (Ru), strontium (Sr), cobalt (Co), or iron (Fe).
20 . The structure as claimed in claim 16 , wherein the backside metallization structures include metallic backside power rails.