Semiconductor packages and methods of manufacturing thereof
A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration. The second substrate has a second width along the horizontal direction, where the second width is greater than the first width.
1 . A method, comprising:
forming a semiconductor die including a plurality of devices over a first substrate, wherein the first substrate includes a dopant at a first concentration;
bonding a backside of the first substrate to a second substrate, wherein the second substrate includes the dopant at a second concentration greater than the first concentration;
singulating the semiconductor die to form a semiconductor package; and
trimming the semiconductor package such that the first substrate has a first width and the second substrate has a second width that is greater than the first width,
wherein the first substrate includes a first semiconductor material and the second substrate includes a second semiconductor material having a different crystal structure than the first semiconductor material.
2 . The method of claim 1 , wherein the first substrate and the second substrate include a same semiconductor material.
3 . The method of claim 1 , wherein the first semiconductor material has an orthorhombic crystal structure and the second semiconductor material has a monoclinic crystal structure.
4 . The method of claim 3 , wherein the first semiconductor material and the second semiconductor material are the same.
5 . The method of claim 1 , wherein the dopant includes boron, carbon, nitrogen, oxygen, sulfur, phosphorus, other dopants, or combinations thereof.
6 . The method of claim 1 , wherein the step of trimming includes:
performing an isotropic etching process using a first gaseous species to form a first recess in the first substrate and a second recess in the second substrate, wherein dimensions of the first recess are greater than dimensions of the second recess;
performing a deposition process to form a polymer layer in the first recess and the second recess using a second gaseous species;
performing an anisotropic etching process using the first gaseous species to remove portions of the polymer layer not deposited in the first recess and the second recess; and
repeating the steps of performing the isotropic etching process, performing the deposition process, and performing the anisotropic etching process to deepen the first recess and the second recess.
7 . The method of claim 6 , wherein the first gaseous species is SF 6 and the second gaseous species is C 4 F 8 .
8 . The method of claim 1 , wherein the trimming step comprising creating a vertical sidewall for the first substrate and a vertical sidewall for the second substrate.
9 . The method of claim 1 , further comprising performing a wet etching process after performing the trimming step.
10 . A method, comprising:
forming a semiconductor die including device features over a first substrate, wherein the first substrate includes a dopant at a first concentration;
fusing a backside of the first substrate with a second substrate, wherein the second substrate includes the dopant at a second concentration greater than the first concentration;
cutting the semiconductor die to form a semiconductor package; and
etching sidewalls of the semiconductor package, wherein the step of etching the sidewalls includes selectively etching the first substrate with respect to the second substrate,
wherein the second substrate is formed of a semiconductor material arranged in a monoclinic structure.
11 . The method of claim 10 , wherein the first substrate and the second substrate both include silicon doped with boron.
12 . The method of claim 10 , wherein the step of fusing includes bonding a first oxide layer on the backside of the first substrate with a second oxide layer on the second substrate.
13 . The method of claim 12 , further comprising performing a wet etching process to remove portions of the first oxide layer and the second oxide layer after the step of etching the sidewalls.
14 . The method of claim 10 , wherein the semiconductor package further includes a hard mask over the device features, and wherein the step of etching the sidewalls removes the hard mask from the semiconductor package.
15 . The method of claim 10 , wherein the step of etching the sidewalls includes cyclically performing an isotropic etching process, a deposition process, and an anisotropic process.
16 . A semiconductor package, comprising:
a die including a plurality of devices over a first substrate, wherein the first substrate includes a dopant at a first concentration, and wherein the first substrate has a first width along a horizontal direction; and
a second substrate fused with the first substrate, wherein the second substrate includes the dopant at a second concentration greater than the first concentration, and wherein the second substrate has a second width along the horizontal direction, the second width being greater than the first width.
17 . The semiconductor package of claim 16 , wherein the plurality of devices includes at least one micro-electromechanical systems (MEMS) device.
18 . The semiconductor package of claim 16 , wherein the first substrate and the second substrate include the same semiconductor material.
19 . The semiconductor package of claim 16 , wherein the dopant includes boron, carbon, nitrogen, oxygen, sulfur, phosphorus, other dopants, or combinations thereof.
20 . The semiconductor package of claim 16 , wherein the first substrate includes a first semiconductor material having an orthorhombic crystal structure and the second substrate includes a second semiconductor material having a monoclinic crystal structure.