Semiconductor structure and manufacturing method thereof
A method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.
1 . A method, comprising:
forming a hard mask stack over a target layer, the hard mask stack comprising a first silicon oxide mask layer, a tungsten carbide mask layer over the first silicon oxide mask layer, and a second silicon oxide mask layer over the tungsten carbide mask layer;
depositing a photoresist layer over the second silicon oxide mask layer of the hard mask stack, the photoresist layer being silicon-free and comprising an organometallic material, wherein the organometallic material has a metal element comprising zirconium, and the organometallic material comprises a metal core bonded to a photo-cleavable ligand having sp 3 -hybridization and a non-photo-cleavable ligand having a crosslinkable functional group;
exposing the photoresist layer to an extreme ultraviolet (EUV) radiation;
developing the exposed photoresist layer to form a photoresist pattern;
forming a spacer on a sidewall of the photoresist pattern;
removing the photoresist pattern; and
after removing the photoresist pattern, patterning the target layer through the spacer and the hard mask stack.
2 . The method of claim 1 , wherein the photoresist layer absorbs the EUV radiation having a wavelength in a range from about 13.3 to about 13.9 nm.
3 . The method of claim 1 , wherein the photoresist layer has a thickness less than about 20 nm.
4 . The method of claim 1 , wherein developing the exposed photoresist layer is performed by a plasma etching process.
5 . The method of claim 4 , wherein the plasma etching process gas is performed by introducing a gas mixture comprising HBr on the exposed photoresist layer.
6 . The method of claim 4 , wherein the plasma etching process is performed by turning on a bias power source having a frequency in a range from about 13.56 MHz to about 2.45 GHz.
7 . The method of claim 1 , wherein the photoresist layer is in contact with a top surface of the second silicon oxide mask layer.
8 . The method of claim 7 , wherein the second silicon oxide mask layer is in contact with a top surface of the tungsten carbide mask layer.
9 . A method, comprising:
forming a hard mask stack over a target layer, the hard mask stack comprising a first dielectric mask layer, a metal-containing second mask layer over the first dielectric mask layer, and a third dielectric mask layer over the metal-containing second mask layer;
depositing a silicon-free metal-containing mandrel layer over the third dielectric mask layer of the hard mask stack, the silicon-free metal-containing mandrel layer serving as a developed resist and having a greater thickness than the first dielectric mask layer, the metal-containing second mask layer, and the third dielectric mask layer, wherein the silicon-free metal-containing mandrel layer comprises a zirconium-containing material, wherein the metal-containing mandrel layer comprises an organometallic material comprising a metal core bonded to a photo-cleavable ligand having sp 3 -hybridization and a non-photo-cleavable ligand having a crosslinkable functional group;
exposing the silicon-free metal-containing mandrel layer by using a reflective reticle to form a pattern having an exposed portion and an unexposed portion;
removing the unexposed portion of the silicon-free metal-containing mandrel layer, while remaining the exposed portion of the silicon-free metal-containing mandrel layer in place;
forming a metal oxide spacer on a sidewall of the exposed portion of the silicon-free metal-containing mandrel layer, wherein the metal oxide spacer comprises titanium oxide and is in contact with the third dielectric mask layer of the hard mask stack;
after forming the metal oxide spacer, removing the exposed portion of the silicon-free metal-containing mandrel layer; and
after removing the exposed portion of the silicon-free metal-containing mandrel layer, patterning the target layer through the metal oxide spacer.
10 . The method of claim 9 , wherein the exposed portion of the silicon-free metal-containing mandrel layer is exposed to a radiation emitted from a droplet in an extreme ultraviolet radiation lithography system, and the silicon-free metal-containing mandrel layer comprises a metal element that has a same composition as the droplet.
11 . The method of claim 9 , wherein removing the unexposed portion of the silicon-free metal-containing mandrel layer is performed by an inductively coupled plasma apparatus, a capacitively coupled plasma apparatus, or a micro wave apparatus.
12 . The method of claim 9 , wherein removing the exposed portion of the silicon-free metal-containing mandrel layer is performed by a dry etching process.
13 . The method of claim 9 , wherein forming the metal oxide spacer comprises:
conformally depositing a metal oxide layer over the exposed portion of the silicon-free metal-containing mandrel layer; and
performing a plasma etching process, by introducing a gas mixture comprising Cl 2 or BCl 3 on the metal oxide layer to remove horizontal portions of the metal oxide layer, such that the metal oxide spacer is formed on the sidewall of the unexposed portion of the silicon-free metal-containing mandrel layer.
14 . The method of claim 9 , wherein the metal oxide spacer comprises titanium oxide.
15 . The method of claim 9 , wherein the silicon-free metal-containing mandrel layer comprises a quencher and a photoacid generator.
16 . The method of claim 9 , wherein the silicon-free metal-containing mandrel layer absorbs an extreme ultraviolet radiation having a wavelength in a range from about 13.3 to about 13.9 nm.
17 . The method of claim 9 , wherein the first dielectric mask layer and the third dielectric mask layer comprise silicon oxide, and the metal-containing second mask layer comprises tungsten carbide.
18 . A method, comprising:
depositing a dielectric layer over a target layer;
depositing a silicon-free metal-containing photoresist layer serving as a mandrel over the dielectric layer, wherein the silicon-free metal-containing photoresist layer has a composition comprising ZrOxCyHz, and the metal-containing photoresist layer comprises a metal core bonded to a photo-cleavable ligand having sp3-hybridization and a non-photo-cleavable ligand having a crosslinkable functional group;
exposing the silicon-free metal-containing photoresist layer to a radiation having a wavelength in a range from about 13.3 nm to about 13.9 nm;
after exposing the silicon-free metal-containing photoresist layer, developing the silicon-free metal-containing photoresist layer to form a silicon-free photoresist pattern;
forming a metal oxide spacer on a sidewall of the silicon-free photoresist pattern, wherein the silicon-free photoresist pattern has a thickness less than 20 nm and maintains a sidewall profile sufficient to support the metal oxide spacer without collapsing;
after forming the metal oxide spacer, removing the silicon-free photoresist pattern;
patterning the dielectric layer by using the metal oxide spacer; and
etching the target layer through the patterned dielectric layer by using the patterned dielectric layer as an etch mask.
19 . The method of claim 18 , wherein the silicon-free metal-containing photoresist layer has a thickness less than about 20 nm.
20 . The method of claim 18 , wherein the dielectric layer serves as a hard mask stack, the hard mask stack comprising a first silicon oxide layer, a tungsten carbide layer over the first silicon oxide layer, and a second silicon oxide layer over the tungsten carbide layer, and wherein a thickness of the first silicon oxide layer is less than a thickness of the tungsten carbide layer, and the thickness of the tungsten carbide layer is less than a thickness of the second silicon oxide layer.