Mitigating pattern collapse
One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
1 . A method for forming a semiconductor structure associated with mitigating pattern collapse, comprising:
etching a first trench within a first dielectric layer;
forming a first metal line within the first trench;
forming a second dielectric layer above the first metal line and the first dielectric layer;
etching a second trench within the second dielectric layer, wherein a portion of the first metal line and a portion of the first dielectric layer are exposed through the second trench;
forming a first metal line barrier within the second trench;
forming a second metal line within the second trench after the forming a first metal line barrier; and
performing an anneal process after the forming a second metal line to form a self-formed barrier from the first metal line barrier and a top barrier layer over the second metal line.
2 . The method of claim 1 , comprising:
forming a second metal line barrier within the first trench before the forming a first metal line, wherein the first metal line is spaced apart from the first dielectric layer by the second metal line barrier.
3 . The method of claim 1 , comprising:
forming an etch stop layer above the first dielectric layer before the forming a second dielectric layer.
4 . The method of claim 1 , wherein an aspect ratio of the second trench is less than four.
5 . The method of claim 1 , wherein an aspect ratio of the second trench is between 2.5 and 3.5.
6 . The method of claim 1 , comprising:
removing a portion of the first metal line barrier over the first metal line to expose at least some of the portion of the first metal line before the forming a second metal line.
7 . The method of claim 1 , comprising, before the etching a second trench:
forming a cap layer above the second dielectric layer; and
forming a hard mask (HM) above the cap layer.
8 . The method of claim 7 , comprising, after the forming a second metal line:
removing at least some of the cap layer;
removing at least some of the HM; and
performing a chemical mechanical planarization (CMP) on at least one of the second dielectric layer or the second metal line.
9 . A method for forming a semiconductor structure associated with mitigating pattern collapse, comprising:
etching a first trench within a first dielectric layer;
forming a first metal line within the first trench;
forming a second dielectric layer above the first metal line and the first dielectric layer;
etching a second trench within the second dielectric layer;
forming a first metal line barrier layer within the second trench;
filling a remainder of the second trench with a first metal material; and
performing an anneal process after the filling a remainder of the second trench with a first metal material to change a composition of the first metal line barrier layer to form a self-formed barrier layer and to form a top barrier layer over the self-formed barrier layer.
10 . The method of claim 9 , wherein the etching a second trench comprises exposing the first metal line.
11 . The method of claim 9 , comprising:
forming an etch stop layer above the first dielectric layer before the forming a second dielectric layer.
12 . The method of claim 9 , wherein an aspect ratio of the second trench is less than four.
13 . The method of claim 9 , wherein an aspect ratio of the second trench is between 2.5 and 3.5.
14 . A method for forming a semiconductor structure associated with mitigating pattern collapse, comprising:
etching a first trench within a first dielectric layer;
forming a first metal line within the first trench;
forming a second dielectric layer above the first metal line and the first dielectric layer;
forming a cap layer above the second dielectric layer;
forming a hard mask (HM) above the cap layer etching a second trench within the second dielectric layer after the forming a HM, wherein a portion of the first metal line and a portion of the first dielectric layer are exposed through the second trench;
forming a second metal line within the second trench; and
after the forming a second metal line:
removing at least some of the cap layer;
removing at least some of the HM; and
performing a chemical mechanical planarization (CMP) on at least one of the second dielectric layer or the second metal line.
15 . The method of claim 14 , comprising performing an anneal process after the forming a second metal line to form a top barrier layer over the second metal line.
16 . The method of claim 14 , comprising:
forming a metal line barrier within the first trench before the forming a first metal line, wherein the first metal line is spaced apart from the first dielectric layer by the metal line barrier.
17 . The method of claim 14 , comprising:
forming a metal line barrier within the second trench before the forming a second metal line; and
removing a portion of the metal line barrier over the first metal line to expose at least some of the portion of the first metal line before the forming a second metal line.
18 . The method of claim 14 , wherein an aspect ratio of the second trench is less than four.
19 . The method of claim 14 , wherein an aspect ratio of the second trench is between 2.5 and 3.5.
20 . The method of claim 14 , comprising:
forming an etch stop layer above the first dielectric layer before the forming a second dielectric layer.