Etch profile control of interconnect structures

1 . A method, comprising:

forming a stack on a substrate, wherein the stack comprises an etch stop layer (ESL), a liner, and a metal oxide layer in contact with the liner, and wherein the substrate comprises a conductive structure;

forming an interlayer dielectric (ILD) layer on the stack, wherein the ILD layer is in contact with the metal oxide layer;

forming a first opening in the ILD layer to expose a top surface of the metal oxide layer;

etching, through the first opening, the metal oxide layer with a first etching process to form a second opening in the metal oxide layer, wherein the second opening exposes a top surface of the liner; and

etching, through the second opening, the liner and the ESL with a second etching process different from the first etching process to form a third opening in the metal oxide layer, the liner, and the ESL, wherein the third opening exposes the conductive structure.

2 . The method of claim 1 , wherein the ESL comprises silicon nitride, silicon oxide, and combinations thereof and is formed on the conductive structure by one of a LPCVD process, a PECVD process, a CVD process, an atomic layer deposition (ALD) process, and a high-aspect-ratio process (HARP).

3 . The method of claim 1 , wherein etching the ESL comprises etching the ESL by a dry etch process using a gas mixture comprising between about 1% and about 5% carbon dioxide.

4 . The method of claim 1 , wherein the liner comprises an oxygen doped carbide material and is formed on the ESL by one of a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, and a CVD process.

5 . The method of claim 1 , wherein etching the liner comprises etching the liner by a dry etch process using a gas mixture comprising fluorocarbon, oxygen, carbon dioxide, nitrogen, and argon.

6 . The method of claim 1 , wherein the metal oxide layer is formed on the liner by a CVD process.

7 . The method of claim 1 , wherein etching the metal oxide layer comprises etching the metal oxide layer by a wet etch process using hydrogen peroxide at a temperature between about 30° C. and about 100° C.

8 . The method of claim 1 , further comprising forming the conductive structure on the substrate, wherein the conductive structure comprises a contact structure, a metal line, and combinations thereof.

9 . The method of claim 1 , further comprising forming an additional conductive structure in the third opening on the conductive structure, wherein the additional conductive structure has a substantially vertical sidewall and is electrically coupled to the conductive structure.

10 . A method, comprising:

etching a capping layer, a first silicon-based layer, and a low temperature oxide (LTO) layer to form a first opening in the first silicon-based layer and the LTO layer while removing the capping layer;

etching, through the first opening, a nitrogen free anti-reflective layer (NFARL) and an interlayer dielectric (ILD) layer below the LTO layer to form a second opening in the NFARL and the ILD layer; and

etching, through the second opening, a metal oxide layer, a liner, and an etch stop layer (ESL) to form a third opening in the ILD, the metal oxide layer, the liner, and the ESL.

11 . The method of claim 10 , further comprising forming the capping layer on the first silicon-based layer by a chemical vapor deposition (CVD) process using a gas mixture comprising silane and oxygen at a temperature between about 200° C. and about 500° C.

12 . The method of claim 10 , wherein etching the capping layer comprises etching the capping layer by a dry etch process using fluorocarbon gas having a flow rate between about 100 sccm and about 400 sccm.

13 . The method of claim 10 , further comprising forming the NFARL on the ILD layer by a chemical vapor deposition (CVD) process using a gas mixture comprising silane and carbon dioxide.

14 . The method of claim 10 , wherein etching the NFARL and the ILD layer comprises etching the NFARL and the ILD layer by a dry etch process using a gas mixture comprising fluorocarbon, oxygen, nitrogen, and argon.

15 . The method of claim 10 , further comprising forming the metal oxide layer on the liner by a CVD process.

16 . The method of claim 10 , wherein etching the metal oxide layer comprises etching the metal oxide layer by a wet etch process using hydrogen peroxide at a temperature between about 30° C. and about 100° C.

17 . The method of claim 10 , further comprising forming a conductive structure on a substrate, wherein the conductive structure comprises a contact structure, a metal line, and combinations thereof.

18 . A method, comprising:

patterning first and second hard mask layers to form a first opening in the first and second hard mask layers;

forming a stack over the first opening, wherein the stack comprises an organic layer, a low temperature oxide (LTO) layer, a first silicon-based layer, and a capping layer, and wherein the organic layer fills the first opening, wherein the first silicon-based layer is between the LTO layer and the capping layer;

etching the stack through the first opening to form a second opening in a nitrogen free anti-reflective layer (NFARL) and an interlayer dielectric (ILD) layer below the LTO layer; and

etching, through the second opening, a metal oxide layer, a liner, and an etch stop layer (ESL) below the ILD to form a third opening in the metal oxide layer, the liner, and the ESL.

19 . The method of claim 18 , wherein etching the metal oxide layer, the liner, and the ESL below the ILD to form the third opening comprises:

etching, through the third opening, the metal oxide layer to form the third opening in the metal oxide; and

etching the liner and ESL through the third opening in the metal oxide to form the third opening in the liner and the ESL.

20 . The method of claim 18 , further comprising patterning the stack to form a fourth opening above the first opening.